- 您现在的位置：买卖IC网 > PDF目录11767 > AD9985BSTZ-110 (Analog Devices Inc)IC INTERFACE 8BIT 110MSPS 80LQFP PDF资料下载
参数资料
| 型号： | AD9985BSTZ-110 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/32页 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE 8BIT 110MSPS 80LQFP |
| 标准包装： | 1 |
| 应用： | 视频 |
| 接口： | 串行 |
| 电源电压： | 2.2 V ~ 3.45 V |
| 封装/外壳： | 80-LQFP |
| 供应商设备封装： | 80-LQFP（14x14） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页
AD9985
Rev. 0 | Page 17 of 32
Hex
Address
Write and
Read or
Read Only
Bits
Default
Value
Register Name
Function
03H
R/W
7:3
01******
Bits [7:6] VCO Range. Selects VCO frequency range. (See PLL
description.)
**001***
Bits [5:3] Charge Pump Current. Varies the current that drives the
low-pass filter. (See PLL description.)
04H
R/W
7:3
10000***
Phase Adjust
ADC Clock Phase Adjustment. Larger values mean more delay.
(1 LSB = T/32)
05H
R/W
7:0
10000000
Clamp
Placement
Places the clamp signal an integer number of clock periods after the
trailing edge of the Hsync signal.
06H
R/W
7:0
10000000
Clamp Duration
Number of clock periods that the clamp signal is actively clamping.
07H
R/W
7:0
00100000
Hsync Output
Pulsewidth
Sets the number of pixel clocks that HSOUT will remain active.
08H
R/W
7:0
10000000
Red Gain
09H
R/W
7:0
10000000
Green Gain
0AH
R/W
7:0
10000000
Blue Gain
Controls ADC input range (contrast) of each respective channel.
Greater values give less contrast.
0BH
R/W
7:1
1000000*
Red Offset
0CH
R/W
7:1
1000000*
Green Offset
0DH
R/W
7:1
1000000*
Blue Offset
Controls dc offset (brightness) of each respective channel. Greater
values decrease brightness.
0EH
R/W
7:0
0*******
Sync Control
Bit 7 – Hsync Polarity Override. (Logic 0 = Polarity determined by chip,
Logic 1 = Polarity set by Bit 6 in Register 0EH.)
*1******
Bit 6 – Hsync Input Polarity. Indicates polarity of incoming Hsync signal
to the PLL. (Logic 0 = Active Low, Logic 1 = Active High.)
**0*****
Bit 5 – Hsync Output Polarity. (Logic 0 = Logic High Sync, Logic 1 =
Logic Low Sync.)
***0****
Bit 4 – Active Hsync Override. If set to Logic 1, the user can select the
Hsync to be used via Bit 3. If set to Logic 0, the active interface is
selected via Bit 6 in Register 14H.
****0***
Bit 3 – Active Hsync Select. Logic 0 selects Hsync as the active sync.
Logic 1 selects Sync-on-Green as the active sync. Note that the
indicated Hsync will be used only if Bit 4 is set to Logic 1 or if both
syncs are active. (Bits 1, 7 = Logic 1 in Register 14H.)
*****0**
Bit 2 – Vsync Output Invert. (Logic 1 = No Invert, Logic 0 = Invert.)
******0*
Bit 1 – Active Vsync Override. If set to Logic 1, the user can select the
Vsync to be used via Bit 0. If set to Logic 0, the active interface is
selected via Bit 3 in Register 14H.
*******0
Bit 0 – Active Vsync Select. Logic 0 selects raw Vsync as the output
Vsync. Logic 1 selects sync separated Vsync as the output Vsync. Note
that the indicated Vsync will be used only if Bit 1 is set to Logic 1.
0FH
R/W
7:1
0*******
Bit 7 – Clamp Function. Chooses between Hsync for Clamp signal or
another external signal to be used for clamping. (Logic 0 = Hsync,
Logic 1 = Clamp.)
*1******
Bit 6 – Clamp Polarity. Valid only with external Clamp signal. (Logic 0 =
Active High, Logic 1 Selects Active Low.)
**0*****
Bit 5 – Coast Select. Logic 0 selects the coast input pins to be used for
the PLL coast. Logic 1 selects Vsync to be used for the PLL coast.
***0****
Bit 4 – Coast Polarity Override. (Logic 0 = Polarity determined by chip,
Logic 1 = Polarity set by Bit 3 in Register 0FH.)
****1***
Bit 3 – Coast Polarity. Selects polarity of external Coast signal. (Logic 0
= Active Low, Logic 1 = Active High.)
*****1**
Bit 2 – Seek Mode Override. (Logic 1 = Allow Low Power Mode, Logic 0
= Disallow Low Power Mode.)
******1*
Bit 1 – PWRDN. Full Chip Power-Down, Active Low. (Logic 0 = Full Chip
Power-Down, Logic 1 = Normal.)
10H
R/W
7:3
10111***
Sync-on-Green
Threshold
Sync-on-Green Threshold. Sets the voltage level of the Sync-on-Green
slicer’s comparator.
相关PDF资料 |
PDF描述 |
|---|---|
| AD9882AKSTZ-100 | IC INTERFACE/DVI 100MHZ 100LQFP |
| AD9882KSTZ-100 | IC INTERFACE/DVI 100MHZ 100LQFP |
| MS27473E16B55PA | CONN PLUG 55POS STRAIGHT W/PINS |
| LTC4305IGN#TR | IC BUFFER BUS 2WR ADDRESS 16SSOP |
| VI-B43-IW-F2 | CONVERTER MOD DC/DC 24V 100W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9985KST-110 | 制造商:Analog Devices 功能描述:110 MSPS/140 MSPS ANLG INTRFC FOR FLAT PNL DISPLAYS 80LQFP - Bulk |
| AD9985KSTZ-110 | 功能描述:IC INTERFACE 8BIT 110MSPS 80LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD9985KSTZ-140 | 功能描述:IC INTERFACE 8BIT 140MSPS 80LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 标准包装:3,000 系列:- 应用:PDA，便携式音频/视频，智能电话 接口:I²C，2 线串口 电源电压:1.65 V ~ 3.6 V 封装/外壳:24-WQFN 裸露焊盘 供应商设备封装:24-QFN 裸露焊盘（4x4） 包装:带卷 (TR) 安装类型:表面贴装 产品目录页面:1015 (CN2011-ZH PDF) 其它名称:296-25223-2 |
| AD9990 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Channel, 14-Bit CCD Signal Processor with V-Driver and Precision Timing |
| AD9990BBCZ | 功能描述:IC CCD SGNL PROCESSOR 112CSPBGA RoHS:是 类别:集成电路 (IC) >> 接口 - 传感器和探测器接口 系列:- 其它有关文件:Automotive Product Guide 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:74 系列:- 类型:触控式传感器 输入类型:数字 输出类型:数字 接口:JTAG，串行 电流 - 电源:100µA 安装类型:表面贴装 封装/外壳:20-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:20-TSSOP 包装:管件 |
发布紧急采购，3分钟左右您将得到回复。