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参数资料
| 型号： | AD9985BSTZ-110 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 2/32页 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE 8BIT 110MSPS 80LQFP |
| 标准包装： | 1 |
| 应用： | 视频 |
| 接口： | 串行 |
| 电源电压： | 2.2 V ~ 3.45 V |
| 封装/外壳： | 80-LQFP |
| 供应商设备封装： | 80-LQFP（14x14） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
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AD9985
Rev. 0 | Page 10 of 32
Pin
Name
Function
SOGIN
Sync-on-Green Input
This input is provided to assist with processing signals with embedded sync, typically on the Green channel. The pin is
connected to a high speed comparator with an internally generated threshold. The threshold level can be programmed in
10 mV steps to any voltage between 10 mV and 330 mV above the negative peak of the input signal. The default voltage
threshold is 150 mV. When connected to an ac-coupled graphics signal with embedded sync, it will produce a noninverting
digital output on SOGOUT. (This is usually a composite sync signal, containing both vertical and horizontal sync information
that must be separated before passing the horizontal sync signal to Hsync.) When not used, this input should be left
unconnected. For more details on this function and how it should be configured, refer to the Sync-on-Green section.
CLAMP
External Clamp Input
This logic input may be used to define the time during which the input signal is clamped to ground. It should be exercised
when the reference dc level is known to be present on the analog input channels, typically during the back porch of the
graphics signal. The CLAMP pin is enabled by setting control bit Clamp Function to 1 (Register 0FH, Bit 7, default is 0). When
disabled, this pin is ignored and the clamp timing is determined internally by counting a delay and duration from the trailing
edge of the Hsync input. The logic sense of this pin is controlled by Clamp Polarity Register 0FH, Bit 6. When not used, this pin
must be grounded and Clamp Function programmed to 0.
COAST
Clock Generator Coast Input (Optional)
This input may be used to cause the pixel clock generator to stop synchronizing with Hsync and continue producing a clock at
its current frequency and phase. This is useful when processing signals from sources that fail to produce horizontal sync pulses
during the vertical interval. The COAST signal is generally not required for PC-generated signals. The logic sense of this pin is
controlled by Coast Polarity (Register 0FH, Bit 3). When not used, this pin may be grounded and Coast Polarity programmed to
1, or tied HIGH (to VD through a 10 k resistor) and Coast Polarity programmed to 0. Coast Polarity defaults to 1 at power-up.
REF
BYPASS
Internal Reference BYPASS
Bypass for the internal 1.25 V band gap reference. It should be connected to ground through a 0.1 F capacitor. The absolute
accuracy of this reference is ±4%, and the temperature coefficient is ±50 ppm, which is adequate for most AD9985 applica-
tions. If higher accuracy is required, an external reference may be employed instead.
MIDSCV
Midscale Voltage Reference BYPASS
Bypass for the internal midscale voltage reference. It should be connected to ground through a 0.1 F capacitor. The exact
voltage varies with the gain setting of the Blue channel.
FILT
External Filter Connection
For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter shown in Figure 8 to this pin.
For optimal performance, minimize noise and parasitics on this node.
POWER SUPPLY
VD
Main Power Supply
These pins supply power to the main elements of the circuit. They should be filtered and as quiet as possible.
VDD
Digital Output Power Supply
A large number of output pins (up to 25) switching at high speed (up to 110 MHz) generates a lot of power supply transients
(noise). These supply pins are identified separately from the VD pins so special care can be taken to minimize output noise
transferred into the sensitive analog circuitry. If the AD9985 is interfacing with lower voltage logic, VDD may be connected to a
lower supply voltage (as low as 2.5 V) for compatibility.
PVD
Clock Generator Power Supply
The most sensitive portion of the AD9985 is the clock generation circuitry. These pins provide power to the clock PLL and help
the user design for optimal performance. The designer should provide quiet, noise-free power to these pins.
GND
Ground
The ground return for all circuitry on-chip. It is recommended that the AD9985 be assembled on a single solid ground plane,
with careful attention given to ground current paths.
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