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参数资料
| 型号： | ADC081500 |
| 厂商： | National Semiconductor Corporation |
| 英文描述： | High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter |
| 中文描述： | 高性能，低功耗，8位，1.5 GSPS的A / D转换 |
| 文件页数： | 24/28页 |
| 文件大小： | 830K |
| 代理商： | ADC081500 |
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2.0 Applications Information
(Continued)
2.4 CONTROL PINS
Six control pins (without the use of the serial interface)
provide a wide range of possibilities in the operation of the
ADC081500 and facilitate its use. These control pins provide
Full-Scale Input Range setting, Self Calibration, Calibration
Delay, Output Edge Synchronization choice, LVDS Output
Level choice and a Power Down feature.
2.4.1 Full-Scale Input Range Setting
The input full-scale range can be selected to be either 650
mV
or 870 mV
, as selected with the FSR control input
(pin 14) in the Normal Mode of operation. In the Extended
Control Mode, the input full-scale range may be set to be
anywhere from 560 mV
P-P
to 840 mV
P-P
. See Section 2.2 for
more information.
2.4.2 Self Calibration
The ADC081500 self-calibration must be run to achieve
specified performance. The calibration procedure is run
upon power-up and can be run any time on command. The
calibration procedure is exactly the same whether there is an
input clock present upon power up or if the clock begins
some time after application of power. The CalRun output
indicator is high while a calibration is in progress. Note that
the DCLK outputs are not active during a calibration cycle.
2.4.2.1 Power-On Calibration
Power-on calibration begins after a time delay following the
application of power. This time delay is determined by the
setting of CalDly, as described in the Calibration Delay Sec-
tion, below.
The calibration process will be not be performed if the CAL
pin is high at power up. In this case, the calibration cycle will
not begin until the on-command calibration conditions are
met. TheADC081500 will function with the CAL pin held high
at power up, but no calibration will be done and performance
will be impaired. A manual calibration, however, may be
performed after powering up with the CAL pin high. See
On-Command Calibration Section 2.4.2.2.
The internal power-on calibration circuitry comes up in an
unknown logic state. If the input clock is not running at power
up and the power on calibration circuitry is active, it will hold
the analog circuitry in power down and the power consump-
tion will typically be less than 200 mW. The power consump-
tion will be normal after the clock starts.
2.4.2.2 On-Command Calibration
On-command calibration may be run at any time. To initiate
an on-command calibration, bring the CAL pin high for a
minimum of 80 input clock cycles after it has been low for a
minimum of 80 input clock cycles. Holding the CAL pin high
upon power up will prevent execution of power-on calibration
until the CAL pin is low for a minimum of 80 input clock
cycles, then brought high for a minimum of another 80 input
clock cycles. The calibration cycle will begin 80 input clock
cycles after the CAL pin is thus brought high. The CalRun
signal should be monitored to determine when the calibra-
tion cycle has completed.
The minimum 80 input clock cycle sequences are required to
ensure that random noise does not cause a calibration to
begin when it is not desired. As mentioned in section 1.1 for
best performance, a self calibration should be performed 20
seconds or more after power up and repeated when the
operating temperature changes significantly relative to the
specific system design performance requirements. ENOB
changes slightly with increasing junction temperature and
can be easily corrected by performing an on-command cali-
bration.
2.4.2.3 Calibration Delay
The CalDly input (pin 127) is used to select one of two delay
times after the application of power to the start of calibration,
as described in Section 1.1.1. The calibration delay values
allow the power supply to come up and stabilize before
calibration takes place. With no delay or insufficient delay,
calibration would begin before the power supply is stabilized
at its operating value and result in non-optimal calibration
coefficients. If the PD pin is high upon power-up, the calibra-
tion delay counter will be disabled until the PD pin is brought
low. Therefore, holding the PD pin high during power up will
further delay the start of the power-up calibration cycle. The
best setting of the CalDly pin depends upon the power-on
settling time of the power supply.
Note that the calibration delay selection is not possible in the
Extended Control mode and the short delay time is used.
2.4.3 Output Edge Synchronization
DCLK signals are available to help latch the converter output
data into external circuitry. The output data can be synchro-
nized with either edge of these DCLK signals. That is, the
output data transition can be set to occur with either the
rising edge or the falling edge of the DCLK signal, so that
either edge of that DCLK signal can be used to latch the
output data into the receiving circuit.
When OutEdge (pin 4) is high, the output data is synchro-
nized with (changes with) the rising edge of the DCLK+ (pin
82). When OutEdge is low, the output data is synchronized
with the falling edge of DCLK+.
At the very high speeds of which the ADC081500 is capable,
slight differences in the lengths of the DCLK and data lines
can mean the difference between successful and erroneous
data capture. The OutEdge pin is used to capture data on
the DCLK edge that best suits the application circuit and
layout.
2.4.4 LVDS Output Level Control
The output level can be set to one of two levels with OutV
(pin3). The strength of the output drivers is greater with OutV
high. With OutV low there is less power consumption in the
output drivers, but the lower output level means decreased
noise immunity.
For short LVDS lines and low noise systems, satisfactory
performance may be realized with the OutV input low. If the
LVDS lines are long and/or the system in which the
ADC081500 is used is noisy, it may be necessary to tie the
OutV pin high.
2.4.6 Power Down Feature
The Power Down pin (PD) suspends device operation and
puts the ADC081500 in a minimum power dissipation state.
See Section 1.1.7 for details on the power down feature.
The digital data (+/-) output pins are put into a high imped-
ance state when the PD pin is high. Upon return to normal
operation, the pipeline will contain meaningless information
and must be flushed.
If the PD input is brought high while a calibration is running,
the device will not go into power down until the calibration
A
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADC081500_06 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter |
| ADC081500_09 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter |
| ADC081500CIYB | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| ADC081500CIYB/NOPB | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| ADC081500DEV | 制造商:NSC 制造商全称:National Semiconductor 功能描述:High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter |
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