参数资料
型号: ADM1041A-EVALZ
厂商: Analog Devices Inc
文件页数: 44/56页
文件大小: 0K
描述: BOARD EVAL FOR ADM1041A
标准包装: 1
主要目的: AC/DC,次级
输出及类型: 1,非隔离
功率 - 输出: 24W
输出电压: 12V
电流 - 输出: 2A
输入电压: 85 ~ 132VAC
板类型: 完全填充
已供物品: 板,线缆,软件
已用 IC / 零件: ADM1041A
ADM1041A
Bit No.
3–2
Name
Soft Start
R/W
R/W
Description
Soft-Start Step
b3 b2 Rise Time
0 0 300 μs
0 1 10 ms
1 0 20 ms
1 1 40 ms
1
0
Address
Trim Lock
R/W
R/W
EEPROM programmable second address bit.
When this bit is set, the trim registers including this register are not writable via SMBus. To
make registers writable again, the trim-lock bit in the EEPROM must first be erased and the
value downloaded using either power-up or test download.
Table 26. Register 11h, Config5. Power-On Default from EEPROM Register 8111h During Power-Up
Bit No.
7
6
5
4–3
2
1
0
Name
Current Limit Disable
PEN Polarity
CBD Polarity
Reserved
OCP Ridethrough
GND_OK Disable
CBD Latch Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Mask effect of OCP to general logic (status flag still gets asserted) when curr_lim_dis = 1.
Sets polarity of PEN output.
Sets polarity of CBD output.
Don’t Care.
Set this bit to 1 when OCP ridethrough is required. A small delay still exists. Refer to Reg 12h.
Disable GROUND_OK input to power management debounce logic.
Select CBD latch mode. 0 = nonlatching; 1 = latching.
Table 27. Register 12h, Config6. Power-On Default from EEPROM Register 8112h During Power-Up
Bit No.
7
Name
Restart Mode
R/W
R/W
Description
Restart mode (rsm). When rsm = 1, the circuit attempts to restart the supply after an
undervoltage or overcurrent at about 1-second intervals.
Latch mode. When rsm = 0, UV and OC faults latch the output off. Cycling PSON or removing
the supply to the IC is then required to reset the latch and permit a restart.
6
Micro AC OK
R/W
Configure microprocessor to control/gate signal from AC_IN_OK to AC_S_OK. See Table 43.
0 = Standalone.
1 = Microprocessor support mode.
5
Micro AC SENSE
R/W
Microproccessor control of AC SENSE . See Table 43.
4–3
OCP Ridethrough
R/W
OCP ridethrough (Reg 11h[2] = 0)
OCP ridethrough (Reg11h[2] = 1)
b4 b3 Period b4 b3 Period
0 0 1 second 0 0 128 μs
0 1 2 seconds 0 1 256 μs
1 0 3 seconds 1 0 384 μs
1 1 4 seconds 1 1 512 μs
2
AC Sense Mode
R/W
AC SENSE mode. 0 means AC_OK is derived from AC SENSE 1, whereas 1 means AC_OK is derived
from AC SENSE 2.
1
0
Micro PS_ON
Current Share Clamp
R/W
R/W
Microprocessor control of pson. See Table 43.
0 = 75%. Set current share clamp release threshold.
1 = 88%.
Table 28. Register 13h, Config7. Power-On Default from EEPROM Register 8113h During Power-Up
Bit No.
7
6
5
4
Name
PEN Polarity
CBD Polarity
DC_OK Polarity
AC_OK Polarity
R/W
R/W
R/W
R/W
R/W
Description
Sets polarity of PEN output.
Sets polarity of CBD output.
Sets polarity of DC_OK output.
Sets polarity of AC_OK output.
Rev. 0 | Page 44 of 56
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