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参数资料
| 型号： | ADM1041AARQZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 34/64页 |
| 文件大小： | 0K |
| 描述： | IC SECONDARY SIDE CTRLR 24QSOP |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 1,000 |
| 应用： | 次级侧控制器 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 电流 - 电源： | 6mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 24-QSOP |
| 包装： | 带卷 (TR) |
| 配用： | ADM1041-EVAL-ND - BOARD EVALUATION ADM1041 |
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ADM1041
BROADCASTING
In a power supply with multiple outputs, it is recommended that
all outputs rise together. Because the SMBus is relatively slow,
simply writing sequentially to the PSON signal in each ADM1041,
for instance, causes a significant delay in the output rise of the
last chip to be written. The ADM1041 avoids this problem by
allocating a common broadcast address that all chips can respond
to. To avoid data collisions, this feature should be used only for
commands that do not initiate a reply.
The peripheral whose address corresponds to the transmit-
ted address responds by pulling the data line low during
the low period before the ninth clock pulse, known as the
Acknowledge bit, and holding it low during the high period
of this clock pulse. All other devices on the bus now remain
idle while the selected device waits for data to be read from
or written to it. If the R/W b it is a 0, then the master writes
to the slave device. If the R/W bit is a 1, the master reads
from the slave device.
SMBus SERIAL INTERFACE
Control of the ADM1041 is carried out via the SMBus. The
ADM1041 is connected to this bus as a slave device under the
control of a master device.
The ADM1041 has a 7-bit serial bus slave address. When the
device is powered up, it does so with a default serial bus address.
The default power-on SMBus address for the device is 1010XXX
binary, the three lowest address bits (A2 to A0) being defined by
the state of the address pin, ADD0, and Bit 1 of Configuration
Register 4 (ADD1). Because ADD0 has three possible states
(tied to V DD , tied to GND, or floating) and Config4 < 1 > can be
high or low, there are a total of six possible addresses, as shown
GENERAL SMBus TIMING
The SMBus specification defines specific conditions for different
types of read and write operation. General SMBus read and
The general SMBus protocol operates as follows:
2.
Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data, followed by an Acknowledge bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal and
remain stable during the high period, because a low-to-
high transition when the clock is high may be interpreted
as a stop signal.
If the operation is a write operation, the first data byte after
the slave address is a command byte. This tells the slave
device what to expect next. It may be an instruction such as
telling the slave device to expect a block write, or it may
simply be a register address that tells the slave where subse-
quent data is to be written.
Because data can flow in only one direction as defined by
the R/W bit, it is not possible to send a command to a slave
device during a read operation. Before doing a read opera-
tion, it might be necessary to first do a write operation to
tell the slave what sort of read operation to expect and/or
the address from which data is to be read.
1.
The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line SDA while the serial clock line SCL remains high.
This indicates that a data stream will follow. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next 8 bits, consisting of a 7-bit
slave address (MSB first), plus a R/W bit, which determines
the direction of the data transfer, that is, whether data is
written to or read from the slave device (0 = write, 1 = read).
3.
When all data bytes have been read or written, stop
conditions are established. In write mode, the master pulls
the data line high during the tenth clock pulse to assert a
stop condition. In read mode, the master device releases
the SDA line during the low period before the ninth clock
pulse, but the slave device does not pull it low. This is
known as No Acknowledge. The master then takes the data
line low during the low period before the tenth clock pulse,
then high during the tenth clock pulse to assert a stop
condition.
Note: If it is required to perform several read or write
operations in succession, the master can send a repeat start
condition instead of a stop condition to begin a new operation.
Rev. A | Page 34 of 64
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADM1041A-EVALZ | 功能描述:BOARD EVAL FOR ADM1041A RoHS:是 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:- 标准包装:1 系列:- 主要目的:DC/DC，步降 输出及类型:1，非隔离 功率 - 输出:- 输出电压:3.3V 电流 - 输出:3A 输入电压:4.5 V ~ 28 V 稳压器拓扑结构:降压 频率 - 开关:250kHz 板类型:完全填充 已供物品:板 已用 IC / 零件:L7981 其它名称:497-12113STEVAL-ISA094V1-ND |
| ADM1041ARQ | 功能描述:IC PWR SUPP MON/LOAD SHAR 24QSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 电源控制器，监视器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 应用:多相控制器 输入电压:- 电源电压:9 V ~ 14 V 电流 - 电源:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:40-WFQFN 裸露焊盘 供应商设备封装:40-TQFN-EP（5x5） 包装:带卷 (TR) |
| ADM1041ARQ-2 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADM1041ARQ-REEL | 制造商:AD 制造商全称:Analog Devices 功能描述:Secondary-Side Controller with Current Share and Housekeeping |
| ADM1041ARQ-REEL7 | 功能描述:IC PWR SUP MON/LOAD SHARE 24QSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 电源控制器，监视器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 应用:多相控制器 输入电压:- 电源电压:9 V ~ 14 V 电流 - 电源:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:40-WFQFN 裸露焊盘 供应商设备封装:40-TQFN-EP（5x5） 包装:带卷 (TR) |
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