参数资料
型号: ADM1041AARQZ
厂商: Analog Devices Inc
文件页数: 33/56页
文件大小: 0K
描述: IC SECONDARY SIDE CTRLR 24QSOP
产品变化通告: Product Discontinuance 27/Oct/2011
标准包装: 56
应用: 次级侧控制器
电源电压: 4.5 V ~ 5.5 V
电流 - 电源: 6mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-SSOP(0.154",3.90mm 宽)
供应商设备封装: 24-QSOP
包装: 管件
配用: ADM1041-EVAL-ND - BOARD EVALUATION ADM1041
ADM1041A
SMBus PROTOCOLS FOR RAM AND EEPROM
The ADM1041A contains volatile registers (RAM) and
nonvolatile EEPROM. RAM occupies the address locations
1
S
2
SLAVE
ADDRESS
3
W A
4
COMMAND A2h
(PAGE ERASE)
5
A
6
EEPROM
ADDRESS
HIGH BYTE
7
A
8
EEPROM
ADDRESS
LOW BYTE
9
A
10
ARBITRARY
DATA
11 12
A P
from 00h to 7Fh, while EEPROM occupies the address locations
(80h OR 81h)
(00h TO FFh)
from 8000h to 813Fh.
The SMBus specification defines several protocols for different
types of read and write operations. The protocols used in the
ADM1041A are described and illustrated in this section. The
following abbreviations are used in the diagrams:
Figure 28. EEPROM Page Erase Operation
Page erasure takes approximately 20 ms. If the EEPROM is
accessed before erasure is complete, the SMBus responds with
No Acknowledge.
Figure 29 shows the peak IDD supply current during an
S
P
R
W
A
A
Start
Stop
Read
Write
Acknowledge
No Acknowledge
EEPROM page erase operation. Decoupling capacitors of 10 μF
and 100 nF are recommended on V DD .
The ADM1041A uses the following SMBus write protocols.
SMBus Erase EEPROM Page Operations
EEPROM memory can be written to only if it is effectively
unprogrammed. Before writing to one or more locations that
are already programmed, the page containing those locations
must be erased. EEPROM ERASE is performed by sending a
page erase command byte (A2h) followed by the page location
of the item to be erased. (There is no need to set an erase bit in
an EEPROM control/status register.)
The EEPROM consists of 16 pages of 32 bytes each; the register
default EEPROM consists of 1 page of 32 bytes starting at
8100h.
Table 7. EEPROM Page Layout
Figure 29. EEPROM Page Erase Peak I DD Current
SMBus Write Operations
Page No.
1
2
3
EEPROM Location
8000h to 801Fh
8020h to 803Fh
8040h to 805Fh
Description
Available FRU
Available FRU
Available FRU
Send Byte
In this operation, the master device sends a single command
byte to a slave device, as follows:
4
5
6
7
8
9
10
11
12
13
8060h to 807Fh
8080h to 809Fh
80A0h to 80BFh
80C0h to 80DFh
80E0h to 80FFh
8100h to 811Fh
8120h to 813Fh
8140h to 815Fh
8160h to 817Fh
8180h to 819Fh
Available FRU
Available FRU
Available FRU
Available FRU
Available FRU
Configuration Boot Registers
ADI Registers
Available FRU
Available FRU
Available FRU
1.
2.
3.
4.
5.
6.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device asserts ACK on SDA.
The master sends a command code.
The slave asserts ACK on SDA.
The master asserts a stop condition on SDA and the
transaction ends.
14
15
16
81A0h to 81BFh
81C0h to 81DFh
81E0h to 81FFh
Available FRU
Available FRU
ADI Registers
In the ADM1041A, the send byte protocol is used to write a
register address to RAM for a subsequent single-byte read from
the same address or block read or write starting at that address.
This is illustrated in Figure 30.
The EEPROM page address consists of the EEPROM address
high byte, 80h for FRU or 81h for register default, and the three
MSBs of the low byte. The lower five bits of the EEPROM
1
S
2
SLAVE
ADDRESS
3
W A
4
RAM
ADDRESS
(00h TO 7Fh)
5 6
A P
address of the low byte are ignored during an erase operation.
Rev. 0 | Page 33 of 56
Figure 30. Setting a RAM Address for Subsequent Read
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