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参数资料
| 型号： | ADMC300BST |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | High Performance DSP-Based Motor Controller |
| 中文描述： | 0-BIT, 12.5 MHz, OTHER DSP, PQFP80 |
| 封装： | PLASTIC, TQFP-80 |
| 文件页数： | 12/42页 |
| 文件大小： | 297K |
| 代理商： | ADMC300BST |
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ADMC300
–12–
REV. B
program and data memory RAM can be loaded from the SROM/
E
2
PROM. After the boot load is complete, program execution
begins at address 0x0060. This is where the first instruction of
the user code should be placed.
If boot loading from an E
2
PROM is unsuccessful, the monitor
code reconfigures SPORT1 as a UART and attempts to receive
commands from an external device on this serial port. The
monitor then waits for a byte to be received over SPORT1,
locks onto the baud rate of the external device (autobaud fea-
ture) and takes in a header word that tells it with what type of
device it is communicating. There are six alternatives:
A UART boot loader such as a Motorola 68HC11 SCI port.
A synchronous slave boot loader (the clock is external).
A synchronous master boot loader (the ADMC300 provides
the clock).
A UART debugger interface.
A synchronous master debugger interface.
A synchronous slave debugger interface.
With the debugger interface, the monitor enters interactive
mode in which it processes commands received from the
external device.
DSP Control Registers
The DSP core has a system control register, SYSCNTL, memory
mapped at DM (0x3FFF). SPORT0 is enabled when Bit 12 is
set, disabled when this bit is cleared. SPORT1 is enabled when
Bit 11 is set, disabled when this bit is cleared. SPORT1 is con-
figured as a serial port when Bit 10 is set, or as flags and inter-
rupt lines when this bit is cleared. For proper operation of the
ADMC300, all other bits in this register must be cleared (which
is their default).
The DSP core has a wait state control register, MEMWAIT,
memory mapped at DM (0x3FFE). For proper operation of the
ADMC300, this register must always contain the value 0x8000
(which is the default).
The configuration of both the SYSCNTL and MEMWAIT
registers of the ADMC300 is shown at the end of the data sheet.
ANALOG-TO-DIGITAL CONVERSION SYSTEM
A functional block diagram of the ADC system of the ADMC300
is shown in Figure 5. The ADC system provides the high perfor-
mance conversion required for precision applications. It integrates
five completely independent analog-to-digital converters based
on sigma-delta conversion technology. Each ADC channel may
V1
V1N
V2
V2N
V3
V3N
V4
V4N
V5
V5N
16-BIT
ADC BANKA
ADC BANKB
REFINA
REFINB
ADCCAL (4…0)
ADCCTRL (15…0)
ADC5 (15…0)
ADC4 (15…0)
ADC3 (15…0)
ADC2 (15…0)
MULTIPLEXER
CONTROL
CONVST(PIO9)
MUX0
MUX1
MUX2
ADCDIVA (11…6)
ADCDIVB (11…6)
ADCSYNC (6…0)
INTERNAL
VOLTAGE
REFERENCE
GENERATOR
UPDATE
ADC1 (15…0)
ADC REGISTER
UPDATE CONTROL
CALIBRATION
MULTIPLEXER
16-BIT
16-BIT
16-BIT
16-BIT
V
REF
DSP DATA
MEMORY
BUS
Figure 5. Functional Block Diagram of ADC System of ADMC300
相关PDF资料 |
PDF描述 |
|---|---|
| ADMC300-ADVEVALKIT | Circular Connector; No. of Contacts:13; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No |
| ADMC328TN | 28-Lead ROM-Based DSP Motor Controller with Current Sense |
| ADMC328TR | 28-Lead ROM-Based DSP Motor Controller with Current Sense |
| ADMC328YN | 28-Lead ROM-Based DSP Motor Controller with Current Sense |
| ADMC328YR | 28-Lead ROM-Based DSP Motor Controller with Current Sense |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADMC300BSTZ | 制造商:Analog Devices 功能描述:DSP Motor Controller 80-Pin TQFP |
| ADMC300-PB | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance DSP-Based Motor Controller |
| ADMC326 | 制造商:AD 制造商全称:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller |
| ADMC326TN | 制造商:AD 制造商全称:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller |
| ADMC326TN-XXX-YY | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MOTOR CONTROLLER |
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