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参数资料
| 型号： | ADMC300BST |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | High Performance DSP-Based Motor Controller |
| 中文描述： | 0-BIT, 12.5 MHz, OTHER DSP, PQFP80 |
| 封装： | PLASTIC, TQFP-80 |
| 文件页数： | 21/42页 |
| 文件大小： | 297K |
| 代理商： | ADMC300BST |
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ADMC300
–21–
REV. B
In each half cycle of the PWM, the timing unit checks the on-
time of each of the six PWM signals. If any of the times is
found to be less than the value specified by the PWMPD regis-
ter, the corresponding PWM signal is turned OFF for the entire
half period and its complementary signal is turned completely
ON.
Consider the example where PWMTM = 200, PWMCHA = 5,
PWMDT = 3, PWMPD = 10 with a CLKOUT of 25 MHz and
operation in single update mode. In this case, the PWM switch-
ing frequency is 62.5 kHz and the dead time is 240 ns. The
permissible on-time of any PWM signal over one-half of any
period is 400 ns. Clearly, for this example, the dead-time
adjusted on-time of the AH signal over half a PWM period is
(5
–
3)
×
40 ns = 80 ns. This is less than the permissible value,
so the timing unit will output a completely OFF (0% duty
cycle) signal on AH. Additionally, the AL signal will be turned
ON for the entire half period (100% duty cycle).
Output Control Unit, PWMSEG Register
The operation of the Output Control Unit is controlled by the
9-bit read/write PWMSEG register. This register controls two
distinct features of the Output Control Unit that are directly
useful in the control of ECM or BDCM.
The PWMSEG register contains three crossover bits; one for
each pair of PWM outputs. Setting Bit 8 of the PWMSEG
register enables the crossover mode for the AH/AL pair of
PWM signals, setting Bit 7 enables crossover on the BH/BL
pair of PWM signals and setting Bit 6 enables crossover on the
CH/CL pair of PWM signals. If crossover mode is enabled for
any pair
of PWM signals, the high-side PWM signal from the
timing unit (AH, for example) is diverted to the associated low-
side output of the Output Control Unit so that the signal will
ultimately appear at the AL pin. Of course, the corresponding
low-side output of the Timing Unit is also diverted to the
complementary high-side output of the Output Control Unit so
that the signal appears at the AH pin. Following a reset, the
three crossover bits are cleared so that the crossover mode is
disabled on all three pairs of PWM signals.
The PWMSEG register also contains six bits (Bits 0 to 5) that
can be used to individually enable or disable each of the six
PWM outputs. The PWM signal of the AL pin is enabled by
setting Bit 5 of the PWMSEG register, while Bit 4 controls AH,
Bit 3 controls BL, Bit 2 controls BH, Bit 1 controls CL, and
Bit 0 controls the CH output. If the associated bit of the
PWMSEG register is set, the corresponding PWM output is
disabled irrespective of the value of the corresponding duty
cycle register. This PWM output signal will remain in the OFF
state as long as the corresponding enable/disable bit of the
PWMSEG register is set. The implementation of this output
enable function is implemented after the crossover function.
Following a reset, all six enable bits of the PWMSEG register
are cleared so that all PWM outputs are enabled by default.
In a manner identical to the duty cycle registers, the PWMSEG
is latched on the rising edge of the PWMSYNC signal so that
changes to this register only become effective at the start of
each PWM cycle in single update mode. In double update
mode, the PWMSEG register can also be updated at the mid-
point of the PWM cycle.
In the control of an ECM only two inverter legs are switched at
any time and often the high-side device in one leg must be
switched ON at the same time as the low-side driver in a second
leg. Therefore, by programming identical duty cycles values for
two PWM channels (say PWMCHA = PWMCHB) and setting
Bit 7 of the PWMSEG register to cross over the BH/BL pair of
PWM signals, it is possible to turn ON the high-side switch of
Phase A and the low-side switch of Phase B at the same time.
In the control of ECM, it is usual that the third inverter leg
(Phase C in this example) be disabled for a number of PWM
cycles. This function is implemented by disabling both the CH
and CL PWM outputs by setting Bits 0 and 1 of the PWMSEG
register. This situation is illustrated in Figure 14, where it can
be seen that both the AH and BL signals are identical, since
PWMCHA = PWMCHB and the crossover bit for phase B is
set. In addition, the other four signals (AL, BH, CH and CL)
have been disabled by setting the appropriate enable/disable
bits of the PWMSEG register. For the situation illustrated in
Figure 14, the appropriate value for the PWMSEG register is
0x00A7. In normal ECM operation, each inverter leg is dis-
abled for certain periods of time so that the PWMSEG register
is changed based on the position of the rotor shaft (motor com-
mutation).
AH
AL
BH
BL
CH
CL
PWMTM
PWMTM
PWMCHA
= PWMCHB
PWMCHA
= PWMCHB
2
PWMDT
2
PWMDT
Figure 14. Example active LO PWM signals suitable for
ECM control, PWMCHA = PWMCHB, crossover BH/BL pair
and disable AL, BH, CH and CL outputs. Operation is in
single update mode.
Gate Drive Unit, PWMGATE Register
The Gate Drive Unit of the PWM controller adds features that
simplify the design of isolated gate drive circuits for PWM
inverters. If a transformer-coupled power device gate drive
amplifier is used then the active PWM signal must be chopped
at a high frequency. The 10-bit read/write PWMGATE register
allows the programming of this high frequency chopping mode.
The chopped active PWM signals may be required for the high-
side drivers only, for the low-side drivers only or for both the
high-side and low-side switches. Therefore, independent con-
trol of this mode for both high- and low-side switches is included
with two separate control bits in the PWMGATE register.
相关PDF资料 |
PDF描述 |
|---|---|
| ADMC300-ADVEVALKIT | Circular Connector; No. of Contacts:13; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADMC300BSTZ | 制造商:Analog Devices 功能描述:DSP Motor Controller 80-Pin TQFP |
| ADMC300-PB | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance DSP-Based Motor Controller |
| ADMC326 | 制造商:AD 制造商全称:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller |
| ADMC326TN | 制造商:AD 制造商全称:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller |
| ADMC326TN-XXX-YY | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MOTOR CONTROLLER |
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