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参数资料
| 型号： | ADMC300BST |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | High Performance DSP-Based Motor Controller |
| 中文描述： | 0-BIT, 12.5 MHz, OTHER DSP, PQFP80 |
| 封装： | PLASTIC, TQFP-80 |
| 文件页数： | 18/42页 |
| 文件大小： | 297K |
| 代理商： | ADMC300BST |
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ADMC300
–18–
REV. B
The PWM controller is driven by a clock at the same frequency
as the DSP instruction rate, CLKOUT, and is capable of gener-
ating two interrupts to the DSP core. One interrupt is generated
on the occurrence of a PWMSYNC pulse and the other is gen-
erated on the occurrence of any PWM shutdown action.
AH
AL
PWMCHA (15
…
0)
PWMCHB (15
…
0)
PWMCHC (15
…
0)
PWMSEG
(8
…
0)
PWMGATE
(8
…
0)
THREE-PHASE
PWM TIMING
UNIT
OUTPUT
CONTROL
UNIT
CLK
SYNC
RESET
SYNC
OR
PIO
PWM
DETECT
GATE
DRIVE
UNIT
CLK
POL
CLKOUT
PWMTM (15
…
0)
PWMDT (9
…
0)
PWMPD(9
…
0)
PWMSYNCWT(7
…
0)
MODECTRL (6)
PWMSWT
(0)
PIOPWM
(11
…
0)
BH
BL
CH
CL
PWMTRIP
PWMSYNC
PWMPOL
:
:
PIO11
TO INTERRUPT
CONTROLLER
PWM
CONFIGURATION
REGISTERS
PWM
DUTY CYCLE
REGISTERS
PWMSYNC
PWMTRIP
PWM SHUTDOWN CONTROLLER
Figure 11. PWM Controller Overview
Three-Phase Timing Unit
The 16-bit three-phase timing unit is the core of the PWM
controller and produces three pairs of pulsewidth modulated
signals with high resolution and minimal processor overhead.
The outputs of this timing unit are active LO such that a low
level is interpreted as a command to turn ON the associated
power device. There are four main configuration registers
(PWMTM, PWMDT, PWMPD and PWMSYNCWT) that
determine the fundamental characteristics of the PWM outputs.
In addition, the operating mode of the PWM (single or double
update mode) is selected by Bit 6 of the MODECTRL register.
These registers, in conjunction with the three 16-bit duty cycle
registers (PWMCHA, PWMCHB and PWMCHC), control the
output of the three-phase timing unit.
PWM Switching Frequency, PWMTM Register
The PWM switching frequency is controlled by the PWM pe-
riod register, PWMTM. The fundamental timing unit of
the PWM controller is t
CK
= 1/f
CLKOUT
where f
CLKOUT
is the
CLKOUT frequency (DSP instruction rate). Therefore, for a
25 MHz CLKOUT, the fundamental time increment is 40 ns.
The value written to the PWMTM register is effectively the
number of t
CK
clock increments in half a PWM period. The
required PWMTM value as a function of the desired PWM
switching frequency (f
PWM
) and is given by:
PWMTM
=
f
CLKOUT
2
×
f
PWM
=
f
CLKIN
f
PWM
Therefore, the PWM switching period, T
S
, can be written as:
T
S
= 2
×
t
CK
×
PWMTM
For example, for a 25 MHz CLKOUT and a desired PWM
switching frequency of 10 kHz (T
S
= 100
μ
s), the correct value
to load into the PWMTM register is:
PWMTM
=
25
×
10
6
2
×
10
×
10
3
=
1250
The largest value that can be written to the 16-bit PWMTM
register is 0xFFFF = 65,535, which corresponds to a minimum
PWM switching frequency of:
f
PWM
,
MIN
=
25
×
10
6
2
×
65,535
=
190.74
Hz
for a CLKOUT frequency of 25 MHz.
PWM Switching Dead Time, PWMDT Register
The second important parameter that must be set up in the
initial configuration of the PWM block is the switching dead
time. This is a short delay time introduced between turning off
one PWM signal (say, AH) and turning on the complementary
signal, AL. This short time delay is introduced to permit the
power switch being turned off (in this case, AH) to completely
recover its blocking capability before the complementary switch
is turned on. This time delay prevents a potentially destructive
short-circuit condition from developing across the dc link
capacitor of a typical voltage source inverter.
The dead time is controlled by the 10-bit, read/write PWMDT
register. There is only one dead-time register that controls the
dead time inserted into all three pairs of PWM output signals.
The dead time, T
D
, is related to the value in the PWMDT regis-
ter by:
T
D
=
PWMDT
×
2
×
t
CK
=
2
×
PWMDT
f
CLKOUT
Therefore, a PWMDT value of 0x00A (= 10), introduces an
800 ns delay between the turn-off on any PWM signal (say, AH)
and the turn-on of its complementary signal (AL). The amount
of the dead time can therefore be programmed in increments of
2t
CK
(or 80 ns for a 25 MHz CLKOUT). The PWMDT register
is a 10-bit register so that its maximum value is 0x3FF (= 1023),
corresponding to a maximum programmed dead time of:
T
D
,
MAX
=
1023
×
2
×
t
CK
=
1023
×
2
×
40
×
10
–
9
=
81.84
μ
s
for a CLKOUT rate of 25 MHz. Obviously, the dead time can
be programmed to be zero by writing 0 to the PWMDT register.
PWM Operating Mode, MODECTRL and SYSSTAT Registers
The PWM controller of the ADMC300 can operate in two
distinct modes; single update mode and double update mode.
The operating mode of the PWM controller is determined by
the state of Bit 6 of the MODECTRL register. If this bit is
cleared the PWM operates in the single update mode. Setting
Bit 6 places the PWM in the double update mode. By default,
following either a peripheral reset or power-on, Bit 6 of the
MODECTRL register is cleared so that the default operating
mode is single update mode.
相关PDF资料 |
PDF描述 |
|---|---|
| ADMC300-ADVEVALKIT | Circular Connector; No. of Contacts:13; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No |
| ADMC328TN | 28-Lead ROM-Based DSP Motor Controller with Current Sense |
| ADMC328TR | 28-Lead ROM-Based DSP Motor Controller with Current Sense |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADMC300BSTZ | 制造商:Analog Devices 功能描述:DSP Motor Controller 80-Pin TQFP |
| ADMC300-PB | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance DSP-Based Motor Controller |
| ADMC326 | 制造商:AD 制造商全称:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller |
| ADMC326TN | 制造商:AD 制造商全称:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller |
| ADMC326TN-XXX-YY | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MOTOR CONTROLLER |
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