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参数资料
| 型号： | ADN2530YCPZ-500R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/20页 |
| 文件大小： | 0K |
| 描述： | IC LASER DRVR 11.3GPBS 16LFCSP |
| 标准包装： | 1 |
| 类型： | 激光二极管驱动器（光纤） |
| 数据速率： | 11.3Gbps |
| 通道数： | 1 |
| 电源电压： | 3.07 V ~ 3.53 V |
| 电流 - 电源： | 27mA |
| 电流 - 调制： | 23mA |
| 电流 - 偏置： | 25mA |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 16-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 16-LFCSP-VQ |
| 包装： | 标准包装 |
| 安装类型： | 表面贴装 |
| 其它名称： | ADN2530YCPZ-500R7DKR |
ADN2530
THEORY OF OPERATION
Data Sheet
As shown in Figure 1, the ADN2530 consists of an input
stage and two voltage-controlled current sources for bias and
modulation. The bias current is available at the IBIAS pin. It is
controlled by the voltage at the BSET pin and can be monitored
50 ?
50 ?
C
C
ADN2530
DATAP
DATAN
at the IBMON pin. The differential modulation current is
available at the IMODP and IMODN pins. It is controlled by
the voltage at the MSET pin. The output stage implements the
active back-termination circuitry for proper transmission line
matching and power consumption reduction. The ADN2530
can drive a load with differential resistance ranging from 35 ?
to 140 ?. The excellent back-termination in the ADN2530
absorbs signal reflections from the TOSA end of the output
transmission lines, enabling excellent optical eye quality to be
achieved even when the TOSA end of the output transmission
lines is significantly misterminated.
INPUT STAGE
The input stage of the ADN2530 converts the data signal applied
DATA SIGNAL SOURCE
Figure 23. AC Coupling the Data Source to the ADN2530 Data Inputs
BIAS CURRENT
The bias current is generated internally using a voltage-to-current
converter consisting of an internal operational amplifier and a
VCC
ADN2530
IBMON
to the DATAP and DATAN pins to a level that ensures proper
operation of the high speed switch. The equivalent circuit of the
BSET
800?
IBIAS
IBMON
IBIAS
VCC
DATAP
200?
200?
10?
50 ?
VCC
GND
Figure 24. Voltage-to-Current Converter Used to Generate IBIAS
DATAN
VCC
50 ?
The BSET to IBIAS voltage-to-current conversion factor is
set at 20 mA/V by the internal resistors, and the bias current is
monitored at the IBMON pin using a current mirror with a gain
equal to 1/20. By connecting a 750 ? resistor between IBMON
and GND, the bias current can be monitored as a voltage across
Figure 22. Equivalent Circuit of the Input Stage
The DATAP and DATAN pins are terminated internally with a
100 ? differential termination resistor. This minimizes signal
reflections at the input that could otherwise lead to degradation
in the output eye diagram. It is not recommended to drive the
ADN2530 with single-ended data signal sources.
The ADN2530 input stage must be ac-coupled to the signal
source to eliminate the need for matching between the common-
mode voltages of the data signal source and the input stage of
the resistor. A low temperature coefficient precision resistor
must be used for the IBMON resistor (R IBMON ). Any error in
the value of R IBMON due to tolerances or drift in its value over
temperature contributes to the overall error budget for the IBIAS
monitor voltage. If the IBMON voltage is being connected to an
ADC for A/D conversion, R IBMON should be placed close to the
ADC to minimize errors due to voltage drops on the ground
plane. See the Design Example section for example calculations
of the accuracy of the IBIAS monitor as a percentage of the
nominal IBIAS value.
the driver (see Figure 23). The ac-coupling capacitors should
have an impedance less than 50 ? over the required frequency
range. Generally, this is achieved using 10 nF to 100 nF
capacitors.
Rev. B | Page 10 of 20
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