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参数资料
| 型号： | ADN2530YCPZ-500R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/20页 |
| 文件大小： | 0K |
| 描述： | IC LASER DRVR 11.3GPBS 16LFCSP |
| 标准包装： | 1 |
| 类型： | 激光二极管驱动器（光纤） |
| 数据速率： | 11.3Gbps |
| 通道数： | 1 |
| 电源电压： | 3.07 V ~ 3.53 V |
| 电流 - 电源： | 27mA |
| 电流 - 调制： | 23mA |
| 电流 - 偏置： | 25mA |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 16-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 16-LFCSP-VQ |
| 包装： | 标准包装 |
| 安装类型： | 表面贴装 |
| 其它名称： | ADN2530YCPZ-500R7DKR |
Data Sheet
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
control the bias and modulation currents. The bias current can
be monitored as a voltage drop across the 750 ? resistor connected
between the IBMON pin and GND. The dc voltage applied to
the CPA pin controls the crosspoint in the output eye diagram.
By tying the CPA pin to VCC, the CPA function is disabled. The
ALS pin allows the user to turn on/off the bias and modulation
currents depending on the logic level applied to the pin. The
data signal source must be connected to the DATAP and DATAN
pins of the ADN2530 using 50 ? transmission lines. The
modulation current outputs, IMODP and IMODN, must be
connected to the load (TOSA) using 100 ? differential (50 ?
single-ended) transmission lines. Table 6 shows recommended
components for the ac-coupling interface between the ADN2530
and TOSA. For additional application information and optical
eye diagram performance data, see the application notes and
reference design for the ADN2530 at www.analog.com .
ADN2530
LAYOUT GUIDELINES
Due to the high frequencies at which the ADN2530 operates,
care should be taken when designing the PCB layout to obtain
optimum performance. Controlled impedance transmission
lines must be used for the high speed signal paths. The length
of the transmission lines must be kept to a minimum to reduce
losses and pattern-dependent jitter. The PCB layout must be
symmetrical both on the DATAP and DATAN inputs and on
the IMODP and IMODN outputs to ensure a balance between
the differential signals. All VCC and GND pins must be connected
to solid copper planes by using low inductance connections.
When the connections are made through vias, multiple vias can
be connected in parallel to reduce the parasitic inductance.
Each GND pin must be locally decoupled to VCC with high
quality capacitors, see Figure 39. If proper decoupling cannot be
achieved using a single capacitor, the user can use multiple
capacitors in parallel for each GND pin. A 20 μF tantalum
capacitor must be used as the general decoupling capacitor for
the entire module. For recommended PCB layouts, including
Table 6.
Component
R1, R2
R3, R4
C3, C4
L6, L7
L2, L3
Value
110 ?
300 ?
100 nF
160 nH
Description
0603 size resistor
0603 size resistor
0402 size capacitor,
Phycomp 223878719849
0603 size inductor,
Murata LQW18ANR16
0603 size chip ferrite bead,
those suitable for XFP modules, contact sales. For guidelines on
the surface-mount assembly of the ADN2530 , consult the
Amkor Technology? “Application Notes for Surface Mount
Assembly of Amkor’s Micro LeadFrame? (MLF?) Packages.”
Murata BLM18HG601
L1, L4, L5, L8
10 μH
0805 size inductor,
Murata LQM21FN100M70L
C8
GND
R5
750 ?
GND
VCC
100nF
V CC
BSET
TP1
C5
10nF
L1
R1
L8
R4
VCC
BSET IBMON IBIAS GND
VCC
VCC
VCC
VCC
L2
L7
Z 0 = 50 ?
Z 0 = 50 ?
Z 0 = 50 ?
DATAP
DATAP
IMODP
Z 0 = 50 ?
C1
ADN2530
GND
Z 0 = 50 ?
C4
Z 0 = 50 ?
TOSA
DATAN
DATAN
IMODN
C2
GND
C3
VCC
VCC
MSET
CPA
ALS
VCC
GND
VCC
L3
L6
VCC
MSET
C6
10nF
L4
R2
L5
R3
+3.3V
VCC
C7
20 μ F
CPA
ALS
GND
VCC
VCC
GND
Figure 39. Typical ADN2530 Application Circuit
Rev. B | Page 15 of 20
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