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参数资料
| 型号： | ADN2530YCPZ-500R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 12/20页 |
| 文件大小： | 0K |
| 描述： | IC LASER DRVR 11.3GPBS 16LFCSP |
| 标准包装： | 1 |
| 类型： | 激光二极管驱动器（光纤） |
| 数据速率： | 11.3Gbps |
| 通道数： | 1 |
| 电源电压： | 3.07 V ~ 3.53 V |
| 电流 - 电源： | 27mA |
| 电流 - 调制： | 23mA |
| 电流 - 偏置： | 25mA |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 16-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 16-LFCSP-VQ |
| 包装： | 标准包装 |
| 安装类型： | 表面贴装 |
| 其它名称： | ADN2530YCPZ-500R7DKR |
ADN2530
This provides excellent transmission line termination while
dissipating less power than a traditional resistor passive back-
termination. No portion of the modulation current flows in the
active back-termination resistance. All of the preset modulation
current IMOD, the range specified in Table 1, flows in the
45
40
35
MAX
Data Sheet
external load. The equivalent circuits for MSET, IMODP, and
IMODN are shown in Figure 31 and Figure 32. The two 50 ?
resistors in Figure 32 are not real resistors. They represent the
active back-termination resistance.
VCC
VCC
30
25
20
MIN
TYP
15
MSET
800 ?
10
10
20
30
40
50
60
70
80
90 100 110 120 130 140
DIFFERENTIAL LOAD RESISTANCE
200 ?
Figure 31. Equivalent Circuit of the MSET Pin
Figure 34. MSET Voltage to Modulation Current Ratio vs.
Differential Load Resistance
Using the resistance of the TOSA, the user can calculate the
VCC
50 ?
IMODN
15 ?
IMODP
15 ?
VCC
50 ?
voltage range that should be applied to the MSET pin to
generate the required modulation current range (see the
example in the Applications Information section).
The circuit used to drive the MSET voltage must be able to
drive the 1 k? resistance of the MSET pin. To be able to drive
23 mA modulation currents through the differential load, the
Figure 32. Equivalent Circuit of the IMODP and IMODN Pins
The recommended configuration of the MSET, IMODP, and
IMODN pins is shown in Figure 33. See Table 6 for recom-
mended components. When the voltage on DATAP is greater
than the voltage on DATAN, the modulation current flows into
the IMODP pin and out of the IMODN pin, generating an
optical Logic 1 level at the TOSA output when the TOSA is
output stage of the ADN2530 (IMODP and IMODN pins)
must be ac-coupled to the load. The voltages at these pins
have a dc component equal to VCC and an ac component with
single-ended peak-to-peak amplitude of IMOD × 50 ?. This
is the case when the load impedance (R TOSA ) is less than
100 ? differential because the transmission line characteristic
impedance sets the peak-to-peak amplitude. For the case where
R TOSA is greater than 100 ?, the single-ended, peak-to-peak
amplitude is IMOD × R TOSA ÷ 2. For proper operation of the
output stage, the voltages at the IMODP and IMODN pins must
IBIAS
VCC
be between the compliance voltage specifications for this pin
over supply, temperature, and modulation current range, as
ADN2530
IMODP
Z 0 = 50 ?
L
C
L
Z 0 = 50 ?
shown in Figure 35. See the Headroom Calculations section for
examples of headroom calculations.
V IMODP, V IMODN
TOSA
Z 0 = 50 ?
C
Z 0 = 50 ?
MSET
IMODN
VCC + 0.7V
VMSET
GND
L
L
NORMAL OPERATION REGION
VCC
VCC
VCC
Figure 33. Recommended Configuration for the
MSET, IMODP, and IMODN Pins
VCC – 0.7V
The ratio between the voltage applied to the MSET pin and the
differential modulation current available at the IMODP and
IMODN pins is a function of the load resistance value, as shown
Rev. B | Page 12 of 20
Figure 35. Allowable Range for the Voltage at IMODP and IMODN
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