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参数资料
| 型号： | ADN2530YCPZ-500R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/20页 |
| 文件大小： | 0K |
| 描述： | IC LASER DRVR 11.3GPBS 16LFCSP |
| 标准包装： | 1 |
| 类型： | 激光二极管驱动器（光纤） |
| 数据速率： | 11.3Gbps |
| 通道数： | 1 |
| 电源电压： | 3.07 V ~ 3.53 V |
| 电流 - 电源： | 27mA |
| 电流 - 调制： | 23mA |
| 电流 - 偏置： | 25mA |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 16-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 16-LFCSP-VQ |
| 包装： | 标准包装 |
| 安装类型： | 表面贴装 |
| 其它名称： | ADN2530YCPZ-500R7DKR |
V BSET =
IBIAS (mA) 10
V MSET =
ADN2530
DESIGN EXAMPLE
This design example covers:
? Headroom calculations for IBIAS, IMODP, and IMODN pins.
? Calculation of the typical voltage required at the BSET
and MSET pins to produce the desired bias and
modulation currents.
? Calculations of the IBIAS monitor accuracy over the IBIAS
current range.
This design example assumes that the impedance of the
TOSA is 60 ?, the forward voltage of the VCSEL at low current
is V F = 1.2 V, IBIAS = 10 mA, IMOD = 10 mA, and VCC = 3.3 V.
Headroom Calculations
To ensure proper device operation, the voltages on the IBIAS,
IMODP, and IMODN pins must meet the compliance voltage
the voltage at the IBIAS pin can be written as
V IBIAS = VCC ? V F ? ( IBIAS × R TOSA ) ? V LA
where:
VCC is the supply voltage.
V F is the forward voltage across the laser at low current.
R TOSA is the resistance of the TOSA.
V LA is the dc voltage drop across L5, L6, L7, and L8.
For proper operation, the minimum voltage at the IBIAS pin
should be greater than 0.55 V, as specified by the minimum
Assuming that the voltage drop across the 50 ? transmission lines
is negligible and that V LA = 0 V, V F = 1.2 V, and IBIAS = 10 mA,
V IBIAS = 3.3 ? 1.2 ? (0.01 × 60) = 1.5 V
V IBIAS = 1.5 V > 0.55 V , which satisfies the requirement
The maximum voltage at the IBIAS pin must be less than the
maximum IBIAS compliance specification as described by
V COMPLIANCE_MAX = VCC ? 0.75 ? 22 × IBIAS (A)
Data Sheet
Assuming the dc voltage drop across L1, L2, L3, and L4 = 0 V
and IMOD = 10 mA, the minimum voltage at the modulation
output pins is equal to
VCC ? ( IMOD × 50)/2 = VCC ? 0.25
VCC ? 0.25 > VCC ? 0.7 V, which satisfies the requirement
The maximum voltage at the modulation output pins is equal to
VCC + ( IMOD × 50)/2 = VCC + 0.25
VCC + 0.25 < VCC + 0.7 V, which satisfies the requirement
Headroom calculations must be repeated for the minimum and
maximum values of the required IBIAS and IMOD ranges to
ensure proper device operation over all operating conditions.
BSET and MSET Pin Voltage Calculation
To set the desired bias and modulation currents, the BSET and
MSET pins of the ADN2530 must be driven with the appropriate
dc voltage. The voltage range required at the BSET pin to generate
the required IBIAS range can be calculated using the BSET voltage
to IBIAS gain specified in Table 1. Assuming that IBIAS = 10 mA
and the typical IBIAS/V BSET ratio of 20 mA/V, the BSET voltage
is given by
= = 0 . 5 V
20 mA/V 20
The BSET voltage range can be calculated using the required
IBIAS range and the minimum and maximum BSET voltage to
The voltage required at the MSET pin to produce the desired
modulation current can be calculated using
IMOD
K
where K is the MSET voltage to IMOD ratio.
The value of K depends on the actual resistance of the TOSA
and can be obtained from Figure 34. For a TOSA resistance of
60 ?, the typical value of K = 24 mA/V. Assuming that IMOD =
10 mA and using the preceding equation, the MSET voltage is
given by
For this example,
V COMPLIANCE_MAX = VCC – 0.75 ? 22 × 0.01 = 2.33 V
V MSET =
IMOD (mA)
24 mA/V
=
10
24
= 0 . 42 V
V IBIAS = 1.5 V < 2.33 V , which satisfies the requirement
To calculate the headroom at the modulation current pins
(IMODP and IMODN), the voltage has a dc component equal
The MSET voltage range can be calculated using the required
IMOD range and the minimum and maximum K values. These can
to VCC due to the ac-coupled configuration and a swing equal
to IMOD × 50 ?, as R TOSA < 100 ?. For proper operation of the
Rev. B | Page 16 of 20
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