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参数资料
| 型号： | ADN2812ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/28页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 32LFCSP |
| 标准包装： | 5,000 |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 输入： | CML |
| 输出： | CML |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.7GHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 带卷 (TR) |
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Data Sheet
ADN2812
Rev. E | Page 19 of 28
The two uses of the reference clock are mutually exclusive. The
reference clock can be used either as an acquisition aid for the
ADN2812 to lock onto data or to measure the frequency of the
incoming data to within 0.01%. (There is the capability to meas-
ure the data rate to approximately ±10% without the use of a
reference clock.) The modes are mutually exclusive because, in
the first use, the user knows the exact data rate and wants to
force the part to lock onto only that data rate; in the second use,
the user does not know the data rate and wants to measure it.
Lock to reference mode is enabled by writing a 1 to I2C Register
Bit CTRLA[0]. Fine data rate readback mode is enabled by
writing a 1 to I2C Register Bit CTRLA[1]. Writing a 1 to both
of these bits at the same time causes an indeterminate state
and is not supported.
Using the Reference Clock to Lock onto Data
Writing CTRLA[0] = 1 puts the ADN2812 into lock-to-REFCLK
(LTR) mode. In this mode, the ADN2812 locks onto a fre-
quency derived from the reference clock according to the
following equation:
Data Rate/2CTRLA[5:2] = REFCLK/2CTRLA[7:6]
The user must know exactly what the data rate is and provide
a reference clock that is a function of this rate. The ADN2812
can still be used as a continuous rate device in this configu-
ration, provided that the user has the ability to provide a
reference clock that has a variable frequency (see the Appli-
cation Note AN-632).
The reference clock can be anywhere between 12.3 MHz and
200 MHz. By default, the ADN2812 expects a reference clock
between 12.3 MHz and 25 MHz. If it is between 25 MHz and
50 MHz, 50 MHz and 100 MHz, or 100 MHz and 200 MHz,
the user needs to configure the ADN2812 to use the correct
reference frequency range by setting two bits of the CTRLA
register, CTRLA[7:6].
Table 11. CTRLA[7:6] Settings
CTRLA[7:6]
Range (MHz)
00
12.3 to 25
01
25 to 50
10
50 to 100
11
100 to 200
Table 12. CTRLA[5:2] Settings
CTRLA[5:2]
Ratio
0000
1
0001
2
n
2n
1000
256
The user can specify a fixed integer multiple of the reference
clock to lock onto using CTRLA[5:2], where CTRLA is set to
the data rate/DIV_FREF and where DIV_FREF represents the
divided-down reference referred to the 12.3 MHz to 25 MHz
band. For example, if the reference clock frequency is 38.88 MHz
and the input data rate is 622.08 Mb/s, CTRLA[7:6] is set to
[01] to give a divided-down reference clock of 19.44 MHz.
CTRLA[5:2] is set to [0101], that is, 5, because
622.08 Mb/s/19.44 MHz = 25
In this mode, if the ADN2812 loses lock for any reason, it
relocks onto the reference clock and continues to output a
stable clock.
While the ADN2812 is operating in LTR mode, if the user ever
changes the reference frequency (the FREF range, CTRLA[7:6] or
the FREF ratio, CTRLA[5:2]), this must be followed by writing a 1
to 0 transition into the CTRLB[5] bit to initiate a new frequency
acquisition.
A frequency acquisition can also be initiated in LTR mode
by writing a 0 to 1 transition into CTRLA[0]; however, it is
recommended that a frequency acquisition be initiated by
writing a 1 to 0 transition into CTRLB[5] as previously
explained.
Using the Reference Clock to Measure Data Frequency
The user can also provide a reference clock to measure the
recovered data frequency, in which case the ADN2812 compares
the frequency of the incoming data to the incoming reference
clock and returns a ratio of the two frequencies to 0.01%
(100 ppm). The accuracy error of the reference clock is added
to the accuracy of the ADN2812 data rate measurement. For
example, if a 100 ppm accuracy reference clock is used, the total
accuracy of the measurement is within 200 ppm.
The reference clock can range from 12.3 MHz to 200 MHz.
The ADN2812 expects a reference clock between 12.3 MHz
and 25 MHz by default. If it is between 25 MHz and 50 MHz,
50 MHz and 100 MHz, or 100 MHz and 200 MHz, the user
needs to configure the ADN2812 to use the correct reference
frequency range by setting two bits of the CTRLA register,
CTRLA[7:6]. Using the reference clock to determine the
frequency of the incoming data does not affect the manner
in which the part locks onto data. In this mode, the reference
clock is used only to determine the frequency of the data. For
this reason, the user does not need to know the data rate to use
the reference clock in this manner.
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