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| 型号： | ADN2812ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/28页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 32LFCSP |
| 标准包装： | 5,000 |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 输入： | CML |
| 输出： | CML |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.7GHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 带卷 (TR) |
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ADN2812
Data Sheet
Rev. E | Page 20 of 28
Prior to reading back the data rate using the reference clock,
Control Register CTRLA Bits[7:6] bits must be set to the
appropriate frequency range with respect to the reference
clock being used. A fine data rate readback is then executed
as follows:
1. Write a 1 to CTRLA[1]. This enables the fine data rate
measurement capability of the ADN2812. This bit is
level-sensitive and does not need to be reset to perform
subsequent frequency measurements.
2. Reset MISC[2] by writing a 1 followed by a 0 to CTRLB[3].
This initiates a new data rate measurement.
3. Read back MISC[2]. If it is 0, the measurement is not
complete. If it is 1, the measurement is complete and the
data rate can be read back on FREQ[22:0]. The time for a
data rate measurement is typically 80 ms.
4. Read back the data rate from Register FREQ2[6:0],
Register FREQ1[7:0], and Register FREQ0[7:0].
Use the following equation to determine the data rate:
fDATARATE = (FREQ[22:0] × fREFCLK)/2(14+ SEL_RATE)
where:
FREQ[22:0] is the reading from FREQ2[6:0] (MSByte),
FREQ1[7:0], and FREQ0[7:0] (LSByte).
fDATARATE is the data rate (Mb/s).
fREFCLK is the REFCLK frequency (MHz).
SEL_RATE is the setting from CTRLA[7:6].
Table 13.
D22
D21...D17
D16
D15
D14...D9
D8
D7
D6...D1
D0
FREQ2[6:0]
FREQ1[7:0]
FREQ0[7:0]
For example, if the reference clock frequency is 32 MHz,
SEL_RATE = 1, because the CTRLA[7:6] setting is [01] and
the reference frequency falls into the 25 MHz to 50 MHz range.
Assume for this example that the input data rate is 2.488 Gb/s
(OC-48). After following Step 1 through Step 4, the value that is
read back on FREQ[22:0] = 0x26E010, which is equal to 2.5477
× 106. Plugging this value into the equation yields
(
)
(
)
Gb/s
488
.
2
/
6
e
32
6
e
5477
.
2
)
1
14
(
=
×
+
If subsequent frequency measurements are required, CTRLA[1]
should remain set to 1. It does not need to be reset. The meas-
urement process is reset by writing a 1 followed by a 0 to
CTRLB[3]. This initiates a new data rate measurement.
Follow Step 2 through Step 4 to read back the new data rate.
Note that a data rate readback is valid only if LOL is low. If LOL
is high, the data rate readback is invalid.
Additional Features Available via the I2C Interface
Coarse Data Rate Readback
The data rate can be read back over the I2C interface to approxi-
mately ±10% without the need of an external reference clock. A
9-bit register, COARSE_RD[8:0], can be read back when LOL
is deasserted. The 8 MSBs of this register are the contents of
the RATE[7:0] register. The LSB of the COARSE_RD register is
Bit MISC[0]. Table 14 provides coarse data rate readback to
within ±10%.
LOS Configuration
The LOS detector output, LOS (Pin 22), can be configured to
be either active high or active low. If CTRLC[2] is set to Logic 0
(default), the LOS pin is active high when a loss of signal condition
is detected. Writing a 1 to CTRLC[2] configures the LOS pin to
be active low when a loss of signal condition is detected.
System Reset
A frequency acquisition can be initiated by writing a 1 followed
by a 0 to the I2C Register Bit CTRLB[5]. This initiates a new
frequency acquisition while keeping the ADN2812 in the
operating mode that it was previously programmed to in
Register CTRL[A], Register CTRL[B], and Register CTRL[C].
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