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参数资料
| 型号： | ADN2850BCPZ250 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/28页 |
| 文件大小： | 0K |
| 描述： | IC DGTL RHEO DL 1024POS 16LFCSP |
| 产品变化通告： | Metal Edit Change 03/Feb/2012 |
| 标准包装： | 1 |
| 接片： | 1024 |
| 电阻（欧姆）： | 250k |
| 电路数： | 2 |
| 温度系数： | 标准值 35 ppm/°C |
| 存储器类型： | 非易失 |
| 接口： | 4 线 SPI（芯片选择） |
| 电源电压： | 3 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VQFN 裸露焊盘，CSP |
| 供应商设备封装： | 16-LFCSP |
| 包装： | 托盘 |
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Data Sheet
ADN2850
Rev. E | Page 17 of 28
ADVANCED CONTROL MODES
The ADN2850 digital resistor includes a set of user
programming features to address the wide number of
applications for these universal adjustment devices.
Key programming features include the following:
Scratchpad programming to any desirable values
Nonvolatile memory storage of the scratchpad RDAC
register value in the EEMEM register
Increment and decrement instructions for the RDAC wiper
register
Left and right bit shift of the RDAC wiper register to
achieve ±6 dB level changes
26 extra bytes of user-addressable nonvolatile memory
Linear Increment and Decrement Instructions
The increment and decrement instructions (Instruction 14,
Instruction 15, Instruction 6, and Instruction 7) are useful for
linear step adjustment applications. These commands simplify
microcontroller software coding by allowing the controller to
send just an increment or decrement command to the device.
The adjustment can be individual or in a ganged resistor
arrangement where both wiper positions are changed at the
same time.
For an increment command, executing Instruction 14
automatically moves the wiper to the next resistance segment
position. The master increment command, Instruction 15,
moves all resistor wipers up by one position.
Logarithmic Taper Mode Adjustment
Four programming instructions produce logarithmic taper
increment and decrement of the wiper position control by
an individual resistor or by a ganged resistor arrangement
where both wiper positions are changed at the same time. The 6
dB increment is activated by Instruction 12 and Instruction 13,
and the 6 dB decrement is activated by Instruction 4 and
Instruction 5. For example, starting with the wiper connected to
Terminal B, executing 11 increment instructions (Command
Instruction 12) moves the wiper in 6 dB steps from 0% of the RBA
(Terminal B) position to 100% of the RBA position of the
ADN2850 10-bit resistor. When the wiper position is near the
maximum setting, the last 6 dB increment instruction causes
the wiper to go to the full-scale 1023 code position. Further 6
dB per increment instructions do not change the wiper position
beyond its full scale (see Table 9).
The 6 dB step increments and 6 dB step decrements are achieved
by shifting the bit internally to the left or right, respectively. The
following information explains the nonideal ±6 dB step adjustment
under certain conditions. Table 9 illustrates the operation of the
shifting function on the RDAC register data bits. Each table row
represents a successive shift operation. Note that the left-shift
12 and 13 instructions were modified such that, if the data in
the RDAC register is equal to zero and the data is shifted left,
the RDAC register is then set to Code 1. Similarly, if the data in
the RDAC register is greater than or equal to midscale and the data
is shifted left, then the data in the RDAC register is automatically
set to full scale. This makes the left-shift function as ideal a
logarithmic adjustment as possible.
The Right-Shift 4 instruction and Right-Shift 5 instruction are
ideal only if the LSB is 0 (ideal logarithmic = no error). If the
LSB is 1, the right-shift function generates a linear half-LSB
error, which translates to a number-of-bits dependent logarithmic
error, as shown in Figure 31. Figure 31 shows the error of the odd
numbers of bits for the ADN2850.
Table 9. Detail Left-Shift and Right-Shift Functions for 6 dB
Step Increment and Decrement
Left-Shift (+6 dB/Step)
Right-Shift(–6 dB/Step)
00 0000 0000
11 1111 1111
00 0000 0001
01 1111 1111
00 0000 0010
00 1111 1111
00 0000 0100
00 0111 1111
00 0000 1000
00 0011 1111
00 0001 0000
00 0001 1111
00 0010 0000
00 0000 1111
00 0100 0000
00 0000 0111
00 1000 0000
00 0000 0011
01 0000 0000
00 0000 0001
10 0000 0000
00 0000 0000
11 1111 1111
00 0000 0000
11 1111 1111
00 0000 0000
Actual conformance to a logarithmic curve between the data
contents in the RDAC register and the wiper position for each
Right-Shift 4 command and Right-Shift 5 command execution
contains an error only for odd numbers of bits. Even numbers of
bits are ideal. Figure 31 shows plots of log error [20 × log10
(error/code)] for the ADN2850. For example, Code 3 log error =
20 × log10 (0.5/3) = 15.56 dB, which is the worst case. The log
error plot is more significant at the lower codes (see Figure 31).
CODE (From 1 to 1023 by 2.0 × 103)
0
G
A
IN
(d
B
)
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
0
–40
–20
–60
–80
0
2
6
0
-0
4
3
Figure 31. Log Error Conformance for Odd Numbers of Bits Only
(Even Numbers of Bits Are Ideal)
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