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| 型号： | ADP1821ARQZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/24页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 16-QSOP |
| 标准包装： | 1 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 720kHz |
| 占空比： | 90% |
| 电源电压： | 3.7 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 包装： | 标准包装 |
| 产品目录页面： | 791 (CN2011-ZH PDF) |
| 其它名称： | ADP1821ARQZ-R7DKR |
ADP1821
SETTING THE CURRENT LIMIT
The current-limit comparator measures the voltage across the
low-side MOSFET to determine the load current.
ADP1821
DH
V IN
M1
L
V OUT
The current limit is set through the current-limit resistor, R CL .
M2
C OUT
CSL, the current sense pin, sources 50 μA through R CL . This
creates an offset voltage of R CL multiplied by the 50 μA CSL
DL
CSL
R LO
R HI
current. When the drop across the low-side MOSFET R DSON is
equal to or greater than this offset voltage, the ADP1821 flags
a current-limit event.
Because the CSL current and the MOSFET R DSON vary over process
and temperature, the minimum current limit should be set to
ensure that the system can handle the maximum desired load
current. To do this, use the peak current in the inductor, which
is the desired current-limit level plus the ripple current, the
maximum R DSON of the MOSFET at its highest expected tem-
perature, and the minimum CSL current.
Figure 15. Short-Circuit Current Foldback Scheme
Because the buck converter is usually running at a fairly high
current, PCB layout and component placement may affect
the current-limit setting. An iteration of the R CL or R LO and R HI
values may be required for a particular board layout and MOSFET
selection. If alternate MOSFETs are substituted at some point in
production, these resistor values may also need an iteration.
FEEDBACK VOLTAGE DIVIDER
The output regulation voltage is set through the feedback voltage
R CL =
I LPK R DSON ( MAX )
42 μA
(15)
divider. The output voltage is reduced through the voltage
divider and drives the FB feedback input. The regulation
where I LPK is the peak inductor current.
When an overcurrent event occurs, the overcurrent comparator
prevents switching cycles until the rectifier current has decayed
below the threshold. The overcurrent comparator is blanked for
the first 100 ns of the synchronous rectifier cycle to prevent
switch node ringing from falsely tripping the current limit. The
ADP1821 senses the current limit during the off cycle. When
the current-limit condition occurs, the output behaves like a
threshold at FB is 0.6 V. The maximum input bias current into
FB is 100 nA. For a 0.15% degradation in regulation voltage and
with 100 nA bias current, the low-side resistor, R BOT , needs to be
less than 9 kΩ, which results in 67 μA of divider current. For
R BOT , use 1 kΩ to 10 kΩ. A larger value resistor can be used, but
results in a reduction in output voltage accuracy due to the
input bias current at the FB pin, whereas lower values cause
increased quiescent current consumption. Choose R TOP to set
the output voltage by using the following equation:
R TOP = R BOT ?
?
?
?
constant current source around the preset current limit. When
the overload condition is removed, the output recovers with the
normal soft start slope and does not overshoot.
? V OUT _ V FB
? V FB
?
?
(18)
In the event of a short circuit, the ADP1821 offers a technique
for implementing a current-limit foldback with the use of an
additional resistor, as shown in Figure 15. Resistor R LO is largely
responsible for setting the foldback current limit during a short
circuit, and Resistor R HI is mainly responsible for setting up the
normal current limit. R LO is lower than R HI . These current-limit
sense resistors can be calculated as
where:
R TOP is the high-side voltage divider resistance.
R BOT is the low-side voltage divider resistance.
V OUT is the regulated output voltage.
V FB is the feedback regulation threshold, 0.6 V.
COMPENSATING THE VOLTAGE MODE BUCK
REGULATOR
R LO =
I PKFOLDBACK R DSON ( MAX )
42 μ A
(16)
Assuming the LC filter design is complete, the feedback control sys-
tem can be compensated. Good compensation is critical to proper
R HI =
? 42 μ A
V OUT (17)
R DSON ( MAX )
I LPK
R LO
where:
I PKFOLDBACK is the desired short circuit peak inductor current limit.
I LPK is the peak inductor current limit during normal operation
and is also used in Equation 15.
operation of the regulator. Calculate the quantities in Equation 19
through Equation 47 to derive the compensation values.
The goal is to guarantee that the voltage gain of the buck con-
verter crosses unity at a slope that provides adequate phase margin
for stable operation. Additionally, at frequencies above the cross-
over frequency, f CO , guaranteeing sufficient gain margin and
attenuation of switching noise are important secondary goals.
Rev. C | Page 14 of 24
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADP1821-BL1-EVZ | 制造商:Analog Devices 功能描述:Evaluation Board For Step-Down DC-To-DC Controller 制造商:Analog Devices 功能描述:BLANK ADISIMPOWER EVAL ADP1821 - Boxed Product (Development Kits) |
| ADP1821-BL2-EVZ | 制造商:Analog Devices 功能描述:Evaluation Board For Step-Down DC-To-DC Controller 制造商:Analog Devices 功能描述:BLANK ADISIMPOWER EVAL ADP1821 - Boxed Product (Development Kits) |
| ADP1821-EVAL | 功能描述:电源管理IC开发工具 Evaluation Board I.C. RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
| ADP1822 | 制造商:AD 制造商全称:Analog Devices 功能描述:PWM, Step-Down DC-to-DC Controller with Margining and Tracking |
| ADP1822ARQZ-R7 | 功能描述:IC REG CTRLR BUCK PWM VM 24-QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:75 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:1MHz 占空比:81% 电源电压:4.3 V ~ 13.5 V 降压:是 升压:是 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:0°C ~ 70°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:管件 产品目录页面:1051 (CN2011-ZH PDF) 其它名称:296-2543-5 |
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