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参数资料
| 型号： | ADP1822-EVAL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADP1822 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 1.8V |
| 电流 - 输出： | 10A |
| 输入电压： | 9 ~ 15 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 300kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ADP1822 |
| 相关产品： | ADP1822ARQZ-R7DKR-ND - IC REG CTRLR BUCK PWM VM 24-QSOP ADP1822ARQZ-R7CT-ND - IC REG CTRLR BUCK PWM VM 24-QSOP ADP1822ARQZ-R7TR-ND - IC REG CTRLR BUCK PWM VM 24-QSOP |
R HI =
V OUT
R ONWC
ADP1822
DH
V FB
R DN = ? TOP ? ? 1 ? ? K MDN ? (17)
ADP1822
(14)
I LPK ? 42 μA
R LO
where:
I PKFOLDBACK is the desired short-circuit peak inductor current
limit.
I LPK is the peak inductor current limit during normal operation
V IN
M1
L V OUT
Data Sheet
Choose the low margin resistor by the equation
? R ? ? ?
? K MDN ? ? V OUT ?
where:
R DN is the down-margin resistor.
R TOP is the top voltage divider resistor from FB to the output
voltage.
V FB is the 0.6 V feedback voltage.
V OUT is the nominal output voltage setting.
K MDN is the down-margin as a ratio of the nominal output voltage
(for example, margining 4% down would be K MDN = 0.04).
DL
M2
R LO
R HI
+
C OUT
For example, for an output voltage of 1.0 V and a ±5% margin,
choose
CSL
Figure 18. Short-Circuit Current Foldback Scheme
R BOT = 10 k?
Thus,
(18)
? V ? V FB ?
? ( R TOP )( R BOT ) ?
? ? R TOP + R BOT ? ?
FEEDBACK VOLTAGE DIVIDER
The output regulation voltage is set through the feedback
voltage divider. The output voltage is reduced through the
voltage divider and drives the FB feedback input. The regulation
threshold at FB is 0.6 V. For the low-side resistor of the voltage
divider, R BOT , use 10 k?. A larger value resistor can be used but
results in a reduction in output voltage accuracy. Choose R TOP to
set the output voltage by
and
R UP = = 80 kΩ
? ?
? V FB ?
K MUP
R TOP = R BOT ? OUT ? = 6 . 67 kΩ
(19)
(20)
R TOP = R BOT ? ? OUT
? V ? V FB ?
?
? ( R TOP )( R BOT ) ?
? R TOP + R BOT ?
R UP = (16)
V FB
f CO =
f SW
f ESRZ =
1
2 π ( C OUT ) ( ESR )
? (15)
? V FB ?
where:
R TOP is the high-side voltage divider resistance.
R BOT is the low-side voltage divider resistance.
V OUT is the regulated output voltage.
V FB is the feedback regulation threshold, 0.6 V.
SETTING THE VOLTAGE MARGIN
The output voltage is margined by connecting a resistor from
FB to GND (for the high margin voltage) or FB to the output
voltage (for low margin voltage). The switches for margining
are supplied inside the ADP1822 and are controlled by the
Choose the high margin resistor by
? ?
K MUP
where:
R UP is the up-margin resistor from MUP to GND.
R BOT is the bottom voltage divider resistor from FB to GND.
R TOP is the top voltage divider resistor from FB to the output
voltage.
K MUP is the high voltage margin as a ratio of the output voltage
(for example, margining 4% up would be K MUP = 0.04).
and
? R ? ? ?
R DN = ? TOP ? ? 1 ? ? K MDN ? = 46 . 7 kΩ (21)
? ? ? ?
? K MDN ? ? V OUT ?
COMPENSATING THE REGULATOR
The output of the error amplifier at COMP is used to compensate
the regulation control system. Connect a resistor capacitor (RC)
network from COMP to FB to compensate the regulator.
The first step of selecting the compensation components is
determining the desired regulation-control crossover frequency,
f CO . Choose a crossover frequency approximately 1/10 of the
switching frequency, or
(22)
10
The characteristics of the output capacitor affect the compensation
required to stabilize the regulator. The output capacitor acts
with its ESR to form a zero. Calculate the ESR zero frequency by
(23)
Note that as similar capacitors are placed in parallel, the ESR
zero frequency remains the same.
If f ESRZ ≤ f CO /2, use the ESR zero to stabilize the regulator (see the
feed-forward network to stabilize the regulator (see the
Rev. D | Page 16 of 24
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADP1823 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual, Interleaved, Step-Down DC-to-DC Controller with Tracking |
| ADP1823ACPZ | 制造商:Analog Devices 功能描述:IC CONTROLLER STEP DOWN DUAL SMD |
| ADP1823ACPZ-R7 | 功能描述:IC REG CTRLR BUCK PWM VM 32LFCSP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
| ADP1823-EVAL | 功能描述:BOARD EVAL FOR ADP1823 RoHS:否 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:- 标准包装:1 系列:- 主要目的:DC/DC，步降 输出及类型:1，非隔离 功率 - 输出:- 输出电压:3.3V 电流 - 输出:3A 输入电压:4.5 V ~ 28 V 稳压器拓扑结构:降压 频率 - 开关:250kHz 板类型:完全填充 已供物品:板 已用 IC / 零件:L7981 其它名称:497-12113STEVAL-ISA094V1-ND |
| ADP1828 | 制造商:AD 制造商全称:Analog Devices 功能描述:Synchronous Buck PWM, Step-Down, DC-to-DC Controller |
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