参数资料
型号: ADP1822-EVAL
厂商: Analog Devices Inc
文件页数: 17/24页
文件大小: 0K
描述: BOARD EVALUATION FOR ADP1822
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 1,非隔离
输出电压: 1.8V
电流 - 输出: 10A
输入电压: 9 ~ 15 V
稳压器拓扑结构: 降压
频率 - 开关: 300kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: ADP1822
相关产品: ADP1822ARQZ-R7DKR-ND - IC REG CTRLR BUCK PWM VM 24-QSOP
ADP1822ARQZ-R7CT-ND - IC REG CTRLR BUCK PWM VM 24-QSOP
ADP1822ARQZ-R7TR-ND - IC REG CTRLR BUCK PWM VM 24-QSOP
f PC 2 =
f SW 1
2 π ( C COMP // C C 2 )( R COMP )
f ZC =
f LC 1
2 π ( C COMP )( R COMP )
C COMP =
4
2 π ( f CO )( R COMP )
C COMP ?
6 . 37
( f SW )( R COMP )
DataSheet
then use both the ESR zero and feed-forward zeros to stabilize
the regulator (see the Compensation Using Both the ESR and
In all three cases, it is sometimes beneficial, although not required,
to add an additional compensation capacitor, C C2 , from COMP
to FB to reduce high frequency noise. This capacitor forms an
extra pole in the loop response. Choose this capacitor such that
the pole occurs at approximately 1/2 of the switching frequency, or
= (24)
2
Assuming C COMP >> C C2 , then solving for C C2 ,
ADP1822
or
= (30)
2
Solving for C COMP ,
(31)
In terms of the switching frequency and combining the constants,
(32)
or
C C 2 =
2
2 π ( f SW )( R COMP )
(25)
C COMP =
2
2 π ( f LC )( R COMP )
(33)
Compensation Using the ESR Zero
or whichever is greater.
R COMP
C C2
C COMP
V OUT
Compensation Using Feed-Forward
C C2
COMP
TO
PWM
FB
0.6V
R TOP
R BOT
COMP
R COMP
C COMP
FB
V OUT
R TOP
C FF
R FF
TO
INTERNAL ERROR AMPLIFIER
PWM
0.6V
R BOT
Figure 19. Compensation Using the ESR Zero
( R TOP ) ( V RAMP ) ( f ESRZ )( f CO )
V IN ( f LC ) 2
1
4 . 9 ( R TOP )( f ESRZ )( f SW ) ( L )( C )
( R TOP )( V RAMP )( f ZFF )( f CO )
V IN ( f LC ) 2
( R TOP )( f SW ) 2 ( L )( C )
R COMP ? 0 . 0705 (35)
If the output capacitor ESR zero is sufficiently low (less than or
equal to 1/2 of the crossover frequency), use the ESR to stabilize
the regulator. In this case, use the circuit shown in Figure 19.
Choose the compensation resistor to set the desired crossover
frequency, typically 1/10 of the switching frequency or
R COMP = (26)
where:
R COMP is the compensation resistor.
V RAMP is the internal ramp peak voltage, 1.25 V.
f ESRZ and f CO are the ESR zero and crossover frequencies.
V IN is the dc input voltage.
f LC is the characteristic frequency of the output LC filter, or
f LC = (27)
2 π LC
using known constants
R COMP ? (28)
V IN
Choose the compensation capacitor to set the compensation
zero, f ZC , to the lesser of 1/4 of the crossover frequency or 1/2 of
the LC resonant frequency, or
INTERNAL ERROR AMPLIFIER
Figure 20. Compensation Using Feed-Forward
If the ESR zero is at too high a frequency to be useful in
stabilizing the regulator, add a series RC network, as shown in
Figure 20, in parallel with the top side voltage divider resistor,
R TOP . This adds an additional zero and pole pair that is used to
increase the phase at crossover, thus improving stability.
Choose the feed-forward zero frequency for 1/7 of the crossover
frequency, and the feed-forward pole at 7× the crossover
frequency. This sets the ratio of pole-to-zero frequency of
approximately 50:1 for optimum stability.
Choose the compensation resistor, R COMP , to set the crossover
frequency by
R COMP = (34)
where f ZFF is the feed-forward zero frequency and is 1/7 of the
crossover frequency. Simplify the following equation:
V IN
f
f ZC =
f CO
4
= SW =
40
1
2 π ( C COMP )( R COMP )
(29)
Rev. D | Page 17 of 24
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