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参数资料
| 型号： | ADP1822-EVAL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADP1822 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 1.8V |
| 电流 - 输出： | 10A |
| 输入电压： | 9 ~ 15 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 300kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ADP1822 |
| 相关产品： | ADP1822ARQZ-R7DKR-ND - IC REG CTRLR BUCK PWM VM 24-QSOP ADP1822ARQZ-R7CT-ND - IC REG CTRLR BUCK PWM VM 24-QSOP ADP1822ARQZ-R7TR-ND - IC REG CTRLR BUCK PWM VM 24-QSOP |
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADP1822
BST
DH
SW
SYNC
1
2
3
4
24
23
22
21
NC
PVCC
DL
PGND
FREQ
MAR
TRKN
TRKP
SHDN
5
6
7
8
9
ADP1822
TOP VIEW
(Not to Scale)
20
19
18
17
16
CSL
VCC
MUP
MDN
MSEL
PWGD 10
DGND 11
GND 12
15
14
13
COMP
FB
SS
NC = NO CONNECT
Figure 4. ADP1822 Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
BST
DH
SW
SYNC
FREQ
MAR
TRKN
TRKP
SHDN
PWGD
DGND
GND
SS
FB
COMP
MSEL
Description
High-Side Gate Driver Boost Capacitor Input. A capacitor between SW and BST powers the high-side gate driver
DH. The capacitor is charged through a diode from PVCC when the low-side MOSFET is on. Connect a 0.1 μF or
greater ceramic capacitor from BST to SW and a Schottky diode from PVCC to BST to power the high-side gate
driver.
High-Side Gate Driver Output. Connect DH to the gate of the external high-side N-channel MOSFET switch.
DH is powered from the capacitor between SW and BST and its voltage swings between V SW and V BST .
Power Switch Node. SW is the power switching node. Connect the source of the high-side N-channel MOSFET
switch and the drain of the low-side N-channel MOSFET synchronous rectifier to SW. SW powers the output
through the output LC filter.
Frequency Synchronization Input. Drive SYNC with an external 300 kHz to 1.2 MHz signal to synchronize the
converter switching frequency to the applied signal. The maximum SYNC frequency is limited to 2× the nominal
internal frequency selected by FREQ. Do not leave SYNC unconnected; when not used, connect SYNC to GND.
Frequency Select Input. FREQ selects the converter switching frequency. Drive FREQ low to select 300 kHz, or
high to select 600 kHz. Do not leave FREQ unconnected.
Margin Control Input. MAR is used with MSEL to control output voltage margining. MAR chooses between
high voltage and low voltage margining when MSEL is driven high. If not used, connect MAR to GND.
Tracking Comparator Negative Input. Drive TRKN from the voltage that the ADP1822 output voltage tracks.
TRKN voltage is limited to VCC. See the Output Voltage Tracking section.
Tracking Comparator Positive Input. Drive TRKP from the output voltage. TRKP voltage is limited to VCC.
See the Output Voltage Tracking section.
Active Low DC-to-DC Shutdown Input. Drive SHDN high to turn on the converter. Drive it low to turn it off.
Connect SHDN to VCC for automatic startup.
Open-Drain Power-Good Output. PWGD sinks current to GND when the output voltage is above or below
the regulation voltage. Connect a pull-up resistor from PWGD to VDD for a logical power-good indicator.
Digital Ground. Connect DGND to GND at a single point as close as possible to the IC.
Analog Ground. Connect GND to PGND at a single point as close as possible to the IC.
Soft Start Control Input. A capacitor from SS to GND controls the soft start period. When the output is overloaded,
SS is discharged to prevent excessive input current while the output recovers. Connect a 1 nF to 1 μF capacitor
from SS to GND to set the soft start period. See the Soft Start section.
Voltage Feedback Input. Connect to a resistive voltage divider from the output to FB to set the output voltage.
See the Setting the Output Voltage section.
Compensation Node. Connect a resistor-capacitor network from COMP to FB to compensate the regulation
control system. See the Compensation section.
Margin Select Input. Drive MSEL high to activate the voltage margining feature. Drive MSEL low to regulate
the output voltage to the nominal value. If not used, connect MSEL to GND.
Rev. D | Page 7 of 24
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