参数资料
型号: ADP1822-EVAL
厂商: Analog Devices Inc
文件页数: 8/24页
文件大小: 0K
描述: BOARD EVALUATION FOR ADP1822
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 1,非隔离
输出电压: 1.8V
电流 - 输出: 10A
输入电压: 9 ~ 15 V
稳压器拓扑结构: 降压
频率 - 开关: 300kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: ADP1822
相关产品: ADP1822ARQZ-R7DKR-ND - IC REG CTRLR BUCK PWM VM 24-QSOP
ADP1822ARQZ-R7CT-ND - IC REG CTRLR BUCK PWM VM 24-QSOP
ADP1822ARQZ-R7TR-ND - IC REG CTRLR BUCK PWM VM 24-QSOP
ADP1822
Data Sheet
Pin No.
17
18
19
20
21
22
23
24
Mnemonic
MDN
MUP
VCC
CSL
PGND
DL
PVCC
NC
Description
Margin Down Input. Connect a resistor from MDN to the output voltage to set the low margining voltage.
See the Setting the Voltage Margin section.
Margin Up Input. Connect a resistor from MUP to GND to set the high margining voltage. See the Setting the
Voltage Margin section.
Internal Power Supply Input. VCC powers the internal circuitry. Bypass VCC to GND with 0.1 μF or greater capacitor
connected as close as possible to the IC.
Low-Side Current Sense Input. Connect CSL to SW through a resistor to set the current limit. See the Setting the
Current Limit section.
Power Ground. Connect GND to PGND at a single point as close as possible to the IC.
Low-Side Gate Driver Output. Connect DL to the gate of the low-side N-channel MOSFET synchronous rectifier.
The DL voltage swings between PGND and PVCC.
Internal Gate Driver Power Supply Input. PVCC powers the low-side gate driver DL. Bypass PVCC to PGND with 1
μF or greater capacitor connected as close as possible to the IC.
No Connection. Not internally connected.
Rev. D | Page 8 of 24
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