参数资料
型号: ADP1850ACPZ-R7
厂商: Analog Devices Inc
文件页数: 19/32页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 32LFCSP
标准包装: 1
PWM 型: 电流模式
输出数: 2
频率 - 最大: 1.725MHz
占空比: 90%
电源电压: 2.75 V ~ 20 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 32-WFQFN 裸露焊盘,CSP
包装: 标准包装
其它名称: ADP1850ACPZ-R7DKR
C OUT ?
Data Sheet
OUTPUT CAPACITOR SELECTION
Choose the output bulk capacitor to set the desired output voltage
ripple. The impedance of the output capacitor at the switching
frequency multiplied by the ripple current gives the output
voltage ripple. The impedance is made up of the capacitive
impedance plus the nonideal parasitic characteristics, the
equivalent series resistance (ESR), and the equivalent series
inductance (ESL). The output voltage ripple can be
approximated by
ADP1850
SR, required to satisfy the voltage droop requirement is
approximated by
Δ I STEP
Δ V DROOP × f SW
where:
Δ I STEP is the step load.
Δ V DROOP is the voltage droop at the output.
When a load is suddenly removed from the output, the energy
Δ V OUT ? Δ I L ? R ESR +
?
+ 4 f SW × L ESL ?
?
?
?
1
8 f SW × C OUT
?
?
stored in the inductor rushes into the capacitor, causing the
output to overshoot. The output capacitance required to satisfy
the output overshoot requirement can be approximated by
Δ I STEP 2 L
+ Δ V OVERSHOOT ) 2 ? V OUT 2
where:
Δ V OUT is the output ripple voltage.
Δ I L is the inductor ripple current.
R ESR is the equivalent series resistance of the output capacitor (or
the parallel combination of ESR of all output capacitors).
L ESL is the equivalent series inductance of the output capacitor
(or the parallel combination of ESL of all capacitors).
Solving C OUT in the previous equation yields
C OUT ?
( V OUT
where:
Δ V OVERSHOOT is the overshoot voltage during the step load.
Select the largest output capacitance given by any of the
previous three equations.
MOSFET SELECTION
C OUT ?
Δ I L
8 f SW
×
1
Δ V OUT ? Δ I L R ESR ? 4 Δ I L f SW × L ESL
The choice of MOSFET directly affects the dc-to-dc converter
performance. A MOSFET with low on resistance reduces I 2 R
P C ? ( I LOAD ) 2 × R DSON ? ? OUT
? V ?
?
Usually the capacitor impedance is dominated by ESR. The
maximum ESR rating of the capacitor, such as in electrolytic or
polymer capacitors, is provided in the manufacturer’s data
sheet; therefore, output ripple reduces to
Δ V OUT ? Δ I L × R ESR
Electrolytic capacitors also have significant ESL, on the order of
5 nH to 20 nH, depending on type, size, and geometry. PCB
traces contribute some ESR and ESL, as well. However, using
the maximum ESR rating from the capacitor data sheet usually
provides some margin such that measuring the ESL is not
usually required.
In the case of output capacitors where the impedance of the
ESR and ESL are small at the switching frequency, for instance,
where the output capacitor is a bank of parallel MLCC capaci-
tors, the capacitive impedance dominates and the output
capacitance equation reduces to
losses, and low gate charge reduces transition losses. The
MOSFET should have low thermal resistance to ensure that the
power dissipated in the MOSFET does not result in excessive
MOSFET die temperature.
The high-side MOSFET carries the load current during on time
and usually carries most of the transition losses of the converter.
Typically, the lower the on resistance of the MOSFET, the
higher the gate charge and vice versa. Therefore, it is important
to choose a high-side MOSFET that balances the two losses. The
conduction loss of the high-side MOSFET is determined by the
equation
?
? V IN ?
where:
R DSON is the MOSFET on resistance.
The gate charging loss is approximated by the equation
C OUT ?
Δ I L
8 Δ V OUT × f SW
P G ? V PV × Q G × f SW
where:
Make sure that the ripple current rating of the output capacitors
is greater than the maximum inductor ripple current.
During a load step transient on the output, for instance, when
the load is suddenly increased, the output capacitor supplies the
load until the control loop has a chance to ramp the inductor
current. This initial output voltage deviation results in a voltage
V PV is the gate driver supply voltage.
Q G is the MOSFET total gate charge.
Note that the gate charging power loss is not dissipated in the
MOSFET but rather in the ADP1850 internal drivers. This
power loss should be taken into consideration when calculating
the overall power efficiency.
droop or undershoot. The output capacitance, assuming 0 Ω
Rev. A | Page 19 of 32
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