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参数资料
| 型号： | ADP1850ACPZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/32页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 32LFCSP |
| 标准包装： | 1 |
| PWM 型： | 电流模式 |
| 输出数： | 2 |
| 频率 - 最大： | 1.725MHz |
| 占空比： | 90% |
| 电源电压： | 2.75 V ~ 20 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 包装： | 标准包装 |
| 其它名称： | ADP1850ACPZ-R7DKR |
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ADP1850
Data Sheet
Pin No.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
(EPAD)
Mnemonic
ILIM2
BST2
SW2
DH2
PGND2
DL2
DL1
PGND1
DH1
SW1
BST1
ILIM1
PGOOD1
SS1
RAMP1
COMP1
FB1
TRK1
Exposed Pad
(EPAD)
Description
Current Limit Sense Comparator Inverting Input for Channel 2. Connect a resistor between ILIM2 and SW2 to set
the current limit offset. For accurate current limit sensing, connect ILIM2 to a current sense resistor at the source
of the low-side MOSFET.
Boot-Strapped Upper Rail of High Side Internal Driver for Channel 2. Connect a multilayer ceramic capacitor
(0.1 μF to 0.22 μF) between BST2 and SW2. There is an internal boost rectifier connected between VDL and BST2.
Switch Node for Channel 2. Connect to source of the high-side N-channel MOSFET and the drain of the low-side
N-channel MOSFET of Channel 2.
High-Side Switch Gate Driver Output for Channel 2. Capable of driving MOSFETs with total input capacitance up
to 20 nF.
Power Ground for Channel 2. Ground for internal Channel 2 driver. Differential current is sensed between SW2
and PGND2. Use the Kelvin sensing connection technique between PGND2 and source of the low-side MOSFET.
Low-Side Synchronous Rectifier Gate Driver Output for Channel 2. To set the gain of the current sense amplifier,
connect a resistor between DL2 and PGND2. Capable of driving MOSFETs with a total input capacitance up to 20 nF.
Low-Side Synchronous Rectifier Gate Driver Output for Channel 1. To set the gain of the current sense amplifier,
connect a resistor between DL1 and PGND1. Capable of driving MOSFETs with a total input capacitance up to 20 nF.
Power Ground for Channel 1. Ground for internal Channel 1 driver. Differential current is sensed between SW1
and PGND1. Use the Kelvin sensing connection technique between PGND1 and source of the low-side MOSFET.
High-Side Switch Gate Driver Output for Channel 1. Capable of driving MOSFETs with a total input capacitance
up to 20 nF.
Power Switch Node for Channel 1. Connect to source of the high-side N-channel MOSFET and the drain of the
low-side N-channel MOSFET of Channel 1.
Boot-Strapped Upper Rail of High Side Internal Driver for Channel 1. Connect a multilayer ceramic capacitor
(0.1 μF to 0.22 μF) between BST1 and SW1. There is an internal boost diode or rectifier connected between VDL
and BST1.
Current Limit Sense Comparator Inverting Input for Channel 1. Connect a resistor between ILIM1 and SW1 to set
the current limit offset. For accurate current limit sensing, connect ILIM1 to a current sense resistor at the source
of the low-side MOSFET.
Power Good. Open-drain power-good indicator logic output with an internal 12 kΩ resistor connected between
PGOOD1 and VCCO. PGOOD1 is pulled to ground when the Channel 1 output is outside the regulation window.
An external pull-up resistor is not required.
Soft Start Input for Channel 1. Connect a capacitor from SS1 to AGND to set the soft start period. This node is
internally pulled up to 5 V with a 6.5 μA current source.
Connect a resistor from RAMP1 to VIN to set up a ramp current for slope compensation in Channel 1. The voltage
at RAMP2 is 0.2 V. This pin is high impedance when the channel is disabled.
Compensation Node for Channel 1. Output of Channel 1 error amplifier. Connect a series resistor-capacitor
network from COMP1 to AGND to compensate the regulation control loop.
Output Voltage Feedback for Channel 1. Connect to Output 1 via a resistor divider.
Tracking Input for Channel 1. Connect TRK1 to VCCO if tracking is not used.
Connect the bottom exposed pad of the LFCSP package to the system AGND plane.
Rev. A | Page 8 of 32
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