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| 型号： | ADP1877HC-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 20/32页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION 13A ADP1877 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 2，非隔离 |
| 输出电压： | 1.05V，1.8V |
| 电流 - 输出： | 13A |
| 输入电压： | 6 ~ 14 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 600kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ADP1877 |
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ADP1877
BOOST CAPACITOR SELECTION
To lower system component count and cost, the ADP1877 has a
built-in rectifier (equivalent to the boost diode) between VCCO
and BSTx. Choose a boost ceramic capacitor with values
between 0.1 μF and 0.22 μF, which provides the current for the
high-side driver during switching.
INDUCTOR SELECTION
The output LC filter smoothes the switched voltage at SWx.
Choose an inductor value such that the inductor ripple current
is approximately 1?3 of the maximum dc output load current.
Using a larger value inductor results in a physical size larger
than required, and using a smaller value results in increased
losses in the inductor and/or MOSFET switches and larger
voltage ripples at the output.
Choose the inductor value by the following equation:
Data Sheet
Usually, the impedance is dominated by ESR, such as in
electrolytic or polymer capacitors, at the switching frequency, as
stated in the maximum ESR rating on the capacitor data sheet;
therefore, output ripple reduces to
Δ V OUT ? Δ I L × R ESR
Electrolytic capacitors also have significant ESL, on the order of
5 nH to 20 nH, depending on type, size, and geometry. PCB
traces contribute some ESR and ESL, as well. However, using
the maximum ESR rating from the capacitor data sheet usually
provides some margin such that measuring the ESL is not
usually required.
In the case of output capacitors where the impedance of the ESR
and ESL are small at the switching frequency, for instance,
where the output cap is a bank of parallel MLCC capacitors, the
capacitive impedance dominates and the output capacitance
× OUT
C OUT ?
L =
where:
V IN ? V OUT
f SW × Δ I L
V
V IN
equation reduces to
Δ I L
8 Δ V OUT × f SW
Δ I STEP
C OUT ?
L is the inductor value.
f SW is the switching frequency.
V OUT is the output voltage.
V IN is the input voltage.
Δ I L is the inductor ripple current, typically 1?3 of the maximum
dc load current.
OUTPUT CAPACITOR SELECTION
Choose the output bulk capacitor to set the desired output voltage
ripple. The impedance of the output capacitor at the switching
frequency multiplied by the ripple current gives the output
voltage ripple. The impedance is made up of the capacitive
impedance plus the nonideal parasitic characteristics, the
equivalent series resistance (ESR), and the equivalent series
inductance (ESL). The output voltage ripple can be
approximated with
Make sure that the ripple current rating of the output capacitors
is greater than the maximum inductor ripple current.
During a load step transient on the output, for instance, when
the load is suddenly increased, the output capacitor supplies the
load until the control loop has a chance to ramp the inductor
current. This initial output voltage deviation results in a voltage
droop or undershoot. The output capacitance, assuming 0 ESR,
required to satisfy the voltage droop requirement can be
approximated by
Δ V DROOP × f SW
where:
Δ I STEP is the step load.
Δ V DROOP is the voltage droop at the output.
? Δ I L ? R ESR +
Δ V OUT
8 f SW × C OUT
?
+ 4 f SW × L ESL ?
?
Δ I STEP 2 L
+ Δ V OVERSHOOT ) 2 ? V OUT 2
? 1
?
where:
Δ V OUT is the output ripple voltage.
Δ I L is the inductor ripple current.
?
?
When a load is suddenly removed from the output, the energy
stored in the inductor rushes into the capacitor, causing the
output to overshoot. The output capacitance required to satisfy
the output overshoot requirement can be approximated by
C OUT ?
( V OUT
R ESR is the equivalent series resistance of the output capacitor (or
the parallel combination of ESR of all output capacitors).
L ESL is the equivalent series inductance of the output capacitor
(or the parallel combination of ESL of all capacitors).
Solving C OUT in the previous equation yields
where:
Δ V OVERSHOOT is the overshoot voltage during the step load.
Select the largest output capacitance given by any of the
previous three equations.
C OUT ?
Δ I L
8 f SW
×
1
Δ V OUT ? Δ I L R ESR ? 4 Δ I L f SW × L ESL
Rev. D | Page 20 of 32
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