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| 型号： | ADP1877HC-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/32页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION 13A ADP1877 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 2，非隔离 |
| 输出电压： | 1.05V，1.8V |
| 电流 - 输出： | 13A |
| 输入电压： | 6 ~ 14 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 600kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ADP1877 |
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ADP1877
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
EN1
1
24
SW1
SYNC
VIN
VCCO
VDL
AGND
FREQ
EN2
2
3
4
5
6
7
8
PIN 1
INDICATOR
ADP1877
TOP VIEW
(Not to Scale)
23
22
21
20
19
18
17
DH1
PGND1
DL1
DL2
PGND2
DH2
SW2
NOTES
1. CONNECT THE BOTTOM EXPOSED PAD OF THE
LFCSP PACKAGE TO SYSTEM AGND PLANE.
Figure 4. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
Mnemonic
EN1
SYNC
VIN
VCCO
VDL
AGND
FREQ
EN2
TRK2
FB2
COMP2
RAMP2
SS2
Description
Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 controller, and drive it low to turn off. Tie
EN1 to VIN for automatic startup. For a precision UVLO, put an appropriately sized resistor divider from VIN to
AGND, and tie the midpoint to this pin.
Frequency Synchronization Input. Accepts an external signal between 1× and 2.3× of the internal oscillator
frequency, f OSC , set by the FREQ pin. The controller operates in forced PWM when a signal is detected at SYNC or
when SYNC is high. The resulting switching frequency is ? of the SYNC frequency. When SYNC is low or left
floating, the controller operates in pulse skip mode.
Connect to Main Power Supply. Bypass with a 1 μF or larger ceramic capacitor connected as close to this pin as
possible and PGND.
Output of the Internal Low Dropout Regulator (LDO). The internal circuitry and gate drivers are powered from
VCCO. Bypass VCCO to AGND with a 1 μF or larger ceramic capacitor. The VCCO output is always active, even
during fault conditions and cannot be turned off even if EN1/EN2 is low. For operations at VIN below 5 V, VIN can
be jumped to VCCO. Do not use the LDO to power other auxiliary system loads.
Power Supply for the Low-Side Driver. Bypass VDL to PGND with a 1 μF or greater ceramic capacitor. Connect
VCCO to VDL.
Analog Ground.
Sets the desired operating frequency between 200 kHz and 1.5 MHz with one resistor between FREQ and AGND.
See Table 4 for more details. Connect FREQ to AGND for a preprogrammed 300 kHz or FREQ to VCCO for a 600 kHz
operating frequency.
Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 controller, and drive it low to turn off. Tie
EN2 to VIN for automatic startup. For a precision UVLO, put an appropriately sized resistor divider from VIN to
AGND, and tie the midpoint to this pin.
Tracking Input for Channel 2. If the tracking function is not used, it is recommended to connect TRK2 to VCCO
through a resistor higher than 1 MΩ, or simply connect TRK2 between 0.7 V and 2 V to reduce the bias current
going into the TRK2 pin.
Output Voltage Feedback for Channel 2. Connect to Channel 2 via a resistor divider.
Compensation Node for Channel 2. Output of Channel 2 error amplifier. Connect a series resistor-capacitor
network from COMP2 to AGND to compensate the regulation control loop.
Programmable Current Setting for Slope Compensation of Channel 2. Connect a resistor from RAMP2 to VIN. The
voltage at RAMP2 is 0.2 V.
Soft Start Input for Channel 2. Connect a capacitor from SS2 to AGND to set the soft start period. This node is
internally pulled up to 3.2 V through a 6.5 μA current source.
Rev. D | Page 8 of 32
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