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参数资料
| 型号： | ADP1883ARMZ-1.0-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 22/40页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 10-MSOP |
| 标准包装： | 1 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 45% |
| 电源电压： | 2.75 V ~ 20 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 包装： | 标准包装 |
| 其它名称： | ADP1883ARMZ-1.0-R7DKR |
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ADP1882/ADP1883
SYNCHRONOUS RECTIFIER
The ADP1882/ADP1883 employ an internal lower-side MOSFET
driver to drive the external upper-side and lower-side MOSFETs.
The synchronous rectifier not only improves overall conduction
efficiency but also ensures proper charging to the bootstrap
capacitor located at the upper-side driver input. This is beneficial
during startup to provide a sufficient drive signal to the external
upper-side MOSFET and attain a fast turn on response, which is
essential for minimizing switching losses. The integrated upper-
side and lower-side MOSFET drivers operate in complementary
fashion with built-in anticross conduction circuitry to prevent
unwanted shoot-through current that may potentially damage the
As soon as the forward current through the lower-side
MOSFET decreases to a level where
10 mV = I Q2 × R ON(Q2)
the zero-cross comparator (or I REV comparator) emits a signal to
turn off the lower-side MOSFET. From this point, the slope of the
as the body diode of the lower-side MOSFET begins to conduct
current and continues conducting current until the remaining
energy stored in the inductor has been depleted.
ANOTHER t ON EDGE IS
TRIGGERED WHEN V OUT
FALLS BELOW REGULATION
MOSFETs or reduce efficiency as a result of excessive power loss.
POWER SAVING MODE (PSM) VERSION (ADP1883)
The ADP1883 is the power saving mode version of the ADP1882.
The ADP1883 operates in the discontinuous conduction mode
(DCM) and pulse skips at light load to midload currents. It outputs
pulses, as necessary, to maintain output regulation. Unlike the
continuous conduction mode (CCM), DCM operation prevents
negative current, thus allowing improved system efficiency at
light loads. Current in the reverse direction through this pathway,
however, results in power dissipation and, therefore, a decrease
in efficiency.
SW
LS
I LOAD
0A
t ON
HS AND LS
IN IDLE MODE
ZERO-CROSS COMPARATOR
DETECTS 10mV OFFSET AND
TURNS OFF LS
10mV = R ON × I LOAD
HS
t ON
Figure 76. 10 mV Offset to Ensure Prevention of Negative Inductor Current
The system remains in idle mode until the output voltage drops
from within regulation. A PWM pulse is then produced, turning
on the upper-side MOSFET to maintain system regulation. The
LS
t OFF
HS AND LS ARE OFF
OR IN IDLE MODE
ADP1883 does not have an internal clock; therefore, it switches
purely as a hysteretic controller as described in this section.
TIMER OPERATION
The ADP1882/ADP1883 employ a constant on-time architecture
I LOAD
0A
AS THE INDUCTOR
CURRENT APPROACHES
ZERO CURRENT, THE STATE
MACHINE TURNS OFF THE
LOWER-SIDE MOSFET.
that provides a variety of benefits, including improved load and
line transient responses when compared with a constant (fixed)
frequency current-mode control loop of a comparable loop design.
The constant on-time timer, or t ON timer, senses the high input
Figure 74. Discontinuous Mode of Operation (DCM)
To minimize the chance of negative inductor current buildup,
an on-board, zero-cross comparator turns off all upper-side and
lower-side switching activities when the inductor current
approaches the zero current line, causing the system to enter
voltage (V IN ) and the output voltage (V OUT ) using SW waveform
information to produce an adjustable one-shot PWM pulse that
varies the on time of the upper-side MOSFET in response to
dynamic changes in input voltage, output voltage, and load current
conditions to maintain regulation. It then generates an on-time
(t ON ) pulse that is inversely proportional to V IN .
idle mode, where the upper-side and lower-side MOSFETs are
turned off. To ensure idle mode entry, a 10 mV offset, connected
in series at the SW node, is implemented (see Figure 75).
t ON = K ×
V OUT
V IN
ZERO-CROSS
COMPARATOR
SW
I Q2
where K is a constant that is trimmed using an RC timer product
for the 300 kHz, 600 kHz, and 1.0 MHz frequency options.
10mV
LS
Q2
Figure 75. Zero-Cross Comparator with 10 mV of Offset
Rev. 0 | Page 22 of 40
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