参数资料
型号: ADP1883ARMZ-1.0-R7
厂商: Analog Devices Inc
文件页数: 6/40页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 10-MSOP
标准包装: 1
PWM 型: 电流模式
输出数: 1
频率 - 最大: 1MHz
占空比: 45%
电源电压: 2.75 V ~ 20 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
包装: 标准包装
其它名称: ADP1883ARMZ-1.0-R7DKR

ADP1882/ADP1883
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VIN 1
10
BST
COMP/EN 2
FB 3
GND 4
VDD 5
ADP1882/
ADP1883
TOP VIEW
(Not to Scale)
9
8
7
6
SW
DRVH
PGND
DRVL
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
VIN
COMP/EN
FB
GND
VDD
DRVL
PGND
DRVH
SW
BST
Description
High Input Voltage. Connect VIN to the drain of the upper-side MOSFET.
Output of the Internal Error Amplifier/IC Enable. When this pin functions as EN, applying 0 V to this pin disables the IC.
Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected.
Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground
plane (see the Layout Considerations s ection).
Bias Voltage Supply for the ADP1882/ADP1883 Controller, Including the Output Gate Drivers. A bypass capacitor
of 1 μF directly from this pin to PGND and a 0.1 μF across VDD and GND are recommended.
Drive Output for the External Lower-Side N-Channel MOSFET. This pin also serves as the current-sense gain
setting pin (see Figure 69).
Power GND. Ground for the lower-side gate driver and lower-side N-channel MOSFET.
Drive Output for the External Upper-Side, N-Channel MOSFET.
Switch Node Connection.
Bootstrap for the Upper-Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected
between VDD and BST. A capacitor from BST to SW is required. An external Schottky diode can also be
connected between VDD and BST for increased gate drive capability.
Rev. 0 | Page 6 of 40
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