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参数资料
| 型号： | ADS1298RIZXGT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PBGA64 |
| 封装： | 8 X 8 MM, LEAD FREE, PLASTIC, NFBGA-64 |
| 文件页数： | 36/87页 |
| 文件大小： | 1430K |
| 代理商： | ADS1298RIZXGT |
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START
DRDY
CS
SCLK
DIN
t
UPDATE
DOUT
Hi-Z
RDATACOpcode
StatusRegister+8-ChannelData(216Bits)
NextData
SBAS459H
– JANUARY 2010 – REVISED MAY 2011
START: Start Conversions
This opcode starts data conversions. Tie the START pin low to control conversions by command. If conversions
are in progress this command has no effect. The STOP opcode command is used to stop conversions. If the
START command is immediately followed by a STOP command, there must be a gap of 4 tCLK cycles between
the two commands. When the START opcode is sent to the device, keep the START pin low until the STOP
command is issued. (See the START subsection of the SPI Interface section for more details.) There are no
restrictions on the SCLK rate for this command and it can be issued any time.
STOP: Stop Conversions
This opcode stops conversions. Tie the START pin low to control conversions by command. When the STOP
command is sent, the conversion in progress completes and further conversions are stopped. If conversions are
already stopped, this command has no effect. There are no restrictions on the SCLK rate for this command
and it can be issued any time.
RDATAC: Read Data Continuous
This opcode enables the output of conversion data on each DRDY without the need to issue subsequent read
data opcodes. This mode places the conversion data in the output register and may be shifted out directly. The
read data continuous mode is the default mode of the device and the device defaults to this mode on power-up
and reset.
RDATAC mode is cancelled by the Stop Read Data Continuous command. If the device is in RDATAC mode, a
SDATAC command must be issued before any other commands can be sent to the device. There is no
restriction on the SCLK rate for this command. However, the subsequent data retrieval SCLKs or the SDATAC
opcode command should wait at least 4 tCLK cycles. The timing for RDATAC is shown in Figure 47. As Figure 47
shows, there is a keep out zone of 4 tCLK cycles around the DRDY pulse when this command cannot be issued.
If no data are retrieved from the device, DOUT and DRDY behave similarly in this mode. To retrieve data from
the device after RDATAC command is issued, make sure either the START pin is high or the START command
is issued. Figure 47 shows the recommended way to use the RDATAC command. RDATAC is ideally suited for
applications such as data loggers or recorders where registers are set once and do not need to be re-configured.
(1)
tUPDATE = 4/fCLK. Do not read data during this time.
Figure 47. RDATAC Usage
SDATAC: Stop Read Data Continuous
This opcode cancels the Read Data Continuous mode. There is no restriction on the SCLK rate for this
command, but the subsequent command must wait for 4 tCLK cycles.
Copyright
2010–2011, Texas Instruments Incorporated
41
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