参数资料
型号: ADSP-21061KSZ-133
厂商: Analog Devices Inc
文件页数: 17/52页
文件大小: 0K
描述: IC DSP CONTROLLER 32BIT 240MQFP
产品培训模块: SHARC Processor Overview
标准包装: 1
系列: SHARC®
类型: 浮点
接口: 同步串行端口(SSP)
时钟速率: 33MHz
非易失内存: 外部
芯片上RAM: 128kB
电压 - 输入/输出: 5.00V
电压 - 核心: 5.00V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 240-BFQFP 裸露焊盘
供应商设备封装: 240-MQFP-EP(32x32)
包装: 托盘
Rev. D | Page 24 of 52 | May 2013
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21061 is the
bus master accessing external memory space in asynchronous
access mode. Note that timing for ACK, DATA, RD, WR, and
DMAGx strobe timing parameters only applies to asynchronous
access mode.
Table 12. Memory Read—Bus Master
5 V and 3.3 V
Unit
Parameter
Min
Max
Timing Requirements
tDAD
Address, Selects Delay to Data Valid1, 2
18 + DT+W
ns
tDRLD
RD Low to Data Valid1
12 + 5DT/8 + W
ns
tHDA
Data Hold from Address, Selects3
0.5
ns
tHDRH
Data Hold from RD High3
2.0
ns
tDAAK
ACK Delay from Address, Selects2, 4
15 + 7DT/8 + W
ns
tDSAK
ACK Delay from RD Low4
8 + DT/2 + W
ns
Switching Characteristics
tDRHA
Address, Selects Hold After RD High
0+H
ns
tDARL
Address, Selects to RD Low2
2 + 3DT/8
ns
tRW
RD Pulse Width
12.5 + 5DT/8 + W
ns
tRWR
RD High to WR, RD, DMAGx Low
8 + 3DT/8 + HI
ns
tSADADC
Address, Selects Setup Before ADRCLK High2
0 + DT/4
ns
W = (number of wait states specified in WAIT register) tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
1 Data delay/setup: user must meet t
DAD or tDRLD or synchronous spec tSSDATI.
2 The falling edge of MSx, SW, BMS is referenced.
3 Data hold: user must meet t
HDA or tHDRH or synchronous spec tHSDATI. See Example System Hold Time Calculation on Page 43 for the calculation of hold times given capacitive
and dc loads.
4 ACK delay/setup: user must meet t
DAAK or tDSAK or synchronous specification tSACKC (Table 13 on Page 25) for deassertion of ACK (Low), all three specifications must be met
for assertion of ACK (High).
Figure 14. Memory Read—Bus Master
WR, DMAG
ACK
DATA
RD
ADDRESS
MSX, SW
BMS
tDARL
tRW
tDAD
tSADADC
tDAAK
tHDRH
tHDA
tRWR
tDRLD
ADDRCLK
(OUT)
tDRHA
tDSAK
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