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参数资料
| 型号： | ADSP-21061KSZ-133 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/52页 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 32BIT 240MQFP |
| 产品培训模块： | SHARC Processor Overview |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | 同步串行端口（SSP） |
| 时钟速率： | 33MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 128kB |
| 电压 - 输入/输出： | 5.00V |
| 电压 - 核心： | 5.00V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 240-BFQFP 裸露焊盘 |
| 供应商设备封装： | 240-MQFP-EP（32x32） |
| 包装： | 托盘 |
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Rev. D | Page 16 of 52 | May 2013
EXTERNAL POWER DISSIPATION (5 V)
Total power dissipation has two components, one due to inter-
nal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruc-
tion execution sequence and the data operands involved.
Internal power dissipation is calculated in the following way:
PINT = IDDIN VDD
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
—the number of output pins that switch during each cycle
(O)
—the maximum frequency at which they can switch (f)
—their load capacitance (C)
—their voltage swing (VDD)
and is calculated by:
PEXT = O C VDD
2
f
The load capacitance should include the processor’s package
capacitance (CIN). The switching frequency includes driving
the load high and then back low. Address and data pins can
drive high and low at a maximum rate of 1/(2tCK). The write
strobe can switch every cycle at a frequency of 1/tCK. Select pins
switch at 1/(2tCK), but selects can switch on each cycle.
Example: Estimate PEXT with the following assumptions:
A system with one bank of external data memory RAM
(32-bit)
Four 128k 8 RAM chips are used, each with a load of
10 pF
External data memory writes occur every other cycle, a rate
of 1/(4tCK), with 50% of the pins switching
The instruction cycle rate is 40 MHz (tCK = 25 ns)
The PEXT equation is calculated for each class of pins that can
drive:
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
PTOTAL = PEXT + (IDDIN2 5.0 V)
Note that the conditions causing a worst-case PEXT are different
from those causing a worst-case PINT. Maximum PINT cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching
simultaneously.
Table 4. External Power Calculations
Pin Type
No. of Pins
% Switching
C
f
VDD2
= PEXT
Address
15
50
44.7 pF
10 MHz
25 V
= 0.084 W
MS0
10
44.7 pF
10 MHz
25 V
= 0.000 W
WR
1—
44.7 pF
20 MHz
25 V
= 0.022 W
Data
32
50
14.7 pF
10 MHz
25 V
= 0.059 W
ADDRCLK
1
—
4.7 pF
20 MHz
25 V
= 0.002 W
PEXT = 0.167 W
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