参数资料
型号: ADSP-21065LKSZ-240
厂商: Analog Devices Inc
文件页数: 19/44页
文件大小: 0K
描述: IC DSP CONTROLLR 544KBIT 208MQFP
产品培训模块: SHARC Processor Overview
标准包装: 1
系列: SHARC®
类型: 浮点
接口: 主机接口,串行端口
时钟速率: 60MHz
非易失内存: 外部
芯片上RAM: 64kB
电压 - 输入/输出: 3.30V
电压 - 核心: 3.30V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 208-BFQFP
供应商设备封装: 208-MQFP(28x28)
包装: 托盘
其它名称: ADSP-21065LKSZ240
ADSP-21065LKSZ240-ND
REV. C
ADSP-21065L
–26–
Three-State Timing—Bus Master, Bus Slave,
HBR, SBTS
These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and
the
SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as the SBTS pin.
Parameter
Min
Max
Unit
Timing Requirements:
tSTSCK
SBTS Setup Before CLKIN
7.0 + 8 DT
ns
tHTSCK
SBTS Hold Before CLKIN
1.0 + 8 DT
ns
Switching Characteristics:
tMIENA
Address/Select Enable After CLKIN
1.0 – 2 DT
ns
tMIENS
Strobes Enable After CLKIN
1
–0.5 – 2 DT
ns
tMIENHG
HBG Enable After CLKIN
2.0 – 2 DT
ns
tMITRA
Address/Select Disable After CLKIN
3.0 – 4 DT
ns
tMITRS
Strobes Disable After CLKIN
1
4.0 – 4 DT
ns
tMITRHG
HBG Disable After CLKIN
5.5 – 4 DT
ns
tDATEN
Data Enable After CLKIN
2
10.0 + 5 DT
ns
tDATTR
Data Disable After CLKIN
2
1.0 – 2 DT
7.0 – 2 DT
ns
tACKEN
ACK Enable After CLKIN
2
7.5 + 4 DT
ns
tACKTR
ACK Disable After CLKIN
2
1.0 – 2 DT
6.0 – 2 DT
ns
tMTRHBG
Memory Interface Disable Before
HBG Low3
2.0 + 2 DT
ns
tMENHBG
Memory Interface Enable After
HBG High3
15.75 + DT
ns
NOTES
1Strobes =
RD, WR, SW, DMAG.
2In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
3Memory Interface = Address,
RD, WR, MSx, SW, DMAGx, BMS (in EPROM boot mode).
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