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参数资料
| 型号： | ADSP-21489BSWZ-3B |
| 厂商： | Analog Devices Inc |
| 文件页数： | 68/68页 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 176LQFP |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | EBI/EMI，DAI，I²C，SPI，SPORT，UART/USART |
| 时钟速率： | 350MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 5Mb |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.10V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 176-LQFP 裸露焊盘 |
| 供应商设备封装： | 176-LQFP-EP（24x24） |
| 包装： | 托盘 |
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Rev. B
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Page 9 of 68
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March 2013
The PWM generator is capable of operating in two distinct
modes while generating center-aligned PWM waveforms:
single-update mode or double-update mode. In single-update
mode the duty cycle values are programmable only once per
PWM period. This results in PWM patterns that are symmetri-
cal about the midpoint of the PWM period. In double-update
mode, a second updating of the PWM registers is implemented
at the midpoint of the PWM period. In this mode, it is possible
to produce asymmetrical PWM patterns that produce lower
harmonic distortion in three-phase PWM inverters.
PWM signals can be mapped to the external port address lines
or to the DPI pins.
MediaLB
The automotive models of the ADSP-2148x processors have an
MLB interface which allows the processor to function as a
media local bus device. It includes support for both 3-pin as well
as 5-pin media local bus protocols. It supports speeds up to
1024 FS (49.25 Mbits/sec, FS = 48.1 kHz) and up to 31 logical
channels, with up to 124 bytes of data per media local bus frame.
For a list of automotive models, see Automotive Products on
Digital Applications Interface (DAI)
The digital applications interface (DAI) allows the connection
of various peripherals to any of the DAI pins (DAI_P20–1).
Programs make these connections using the signal routing unit
(SRU).
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon-
nected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with noncon-
figurable signal paths.
The DAI includes eight serial ports, four precision clock genera-
tors (PCG), a S/PDIF transceiver, four ASRCs, and an input
data port (IDP). The IDP provides an additional input path to
the SHARC core, configurable as either eight channels of serial
data, or a single 20-bit wide synchronous parallel data acquisi-
tion port. Each data channel has its own DMA channel that is
independent from the processor’s serial ports.
Serial Ports (SPORTs)
The ADSP-2148x features eight synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog Devices’
AD183x family of audio codecs, ADCs, and DACs. The serial
ports are made up of two data lines, a clock, and frame sync. The
data lines can be programmed to either transmit or receive and
each data line has a dedicated DMA channel.
Serial ports can support up to 16 transmit or 16 receive DMA
channels of audio data when all eight SPORTs are enabled, or
four full duplex TDM streams of 128 channels per frame.
Serial port data can be automatically transferred to and from
on-chip memory/external memory via dedicated DMA chan-
nels. Each of the serial ports can work in conjunction with
another serial port to provide TDM support. One SPORT pro-
vides two transmit signals while the other SPORT provides the
two receive signals. The frame sync and clock are shared.
Serial ports operate in five modes:
Standard serial mode
Multichannel (TDM) mode
I2S mode
Packed I2S mode
Left-justified mode
S/PDIF-Compatible Digital Audio Receiver/Transmitter
The S/PDIF receiver/transmitter has no separate DMA chan-
nels. It receives audio data in serial format and converts it
into a biphase encoded signal. The serial data input to the
receiver/transmitter can be formatted as left-justified, I2S or
right-justified with word widths of 16, 18, 20, or 24 bits.
The serial data, clock, and frame sync inputs to the S/PDIF
receiver/transmitter are routed through the signal routing unit
(SRU). They can come from a variety of sources, such as the
SPORTs, external pins, or the precision clock generators
(PCGs), and are controlled by the SRU control registers.
Asynchronous Sample Rate Converter (SRC)
The asynchronous sample rate converter contains four SRC
blocks and is the same core as that used in the AD1896 192 kHz
stereo asynchronous sample rate converter and provides up to
128 dB SNR. The SRC block is used to perform synchronous or
asynchronous sample rate conversion across independent stereo
channels, without using internal processor resources. The four
SRC blocks can also be configured to operate together to
convert multichannel audio data without phase mismatches.
Finally, the SRC can be used to clean up audio data from jittery
clock sources such as the S/PDIF receiver.
Input Data Port
The IDP provides up to eight serial input channels—each with
its own clock, frame sync, and data inputs. The eight channels
are automatically multiplexed into a single 32-bit by eight-deep
FIFO. Data is always formatted as a 64-bit frame and divided
into two 32-bit words. The serial protocol is designed to receive
audio channels in I2S, left-justified sample pair, or right-justified
mode.
The IDP also provides a parallel data acquisition port (PDAP),
which can be used for receiving parallel data. The PDAP port
has a clock input and a hold input. The data for the PDAP can
be received from DAI pins or from the external port pins. The
PDAP supports a maximum of 20-bit data and four different
packing modes to receive the incoming data.
Precision Clock Generators
The precision clock generators (PCG) consist of four units, each
of which generates a pair of signals (clock and frame sync)
derived from a clock input signal. The units, A B, C, and D, are
identical in functionality and operate independently of each
other. The two signals generated by each unit are normally used
as a serial bit clock/frame sync pair.
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| ADSP-21489BSWZ-4A | 功能描述:IC CCD SIGNAL PROCESSOR 100LQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21489BSWZ-4B | 功能描述:IC CCD SIGNAL PROCESSOR 176LQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21489BSWZ-AX | 制造商:Analog Devices 功能描述:X GRADE SHARC PROCESSOR - Trays |
| ADSP-21489BSWZ-BX | 制造商:Analog Devices 功能描述:X GRADE SHARC PROCESSOR - Trays |
| ADSP-21489KSWZ-3A | 功能描述:IC CCD SIGNAL PROCESSOR 100LQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
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