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| 型号： | ADSP-21489BSWZ-3B |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/68页 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 176LQFP |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | EBI/EMI，DAI，I²C，SPI，SPORT，UART/USART |
| 时钟速率： | 350MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 5Mb |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.10V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 176-LQFP 裸露焊盘 |
| 供应商设备封装： | 176-LQFP-EP（24x24） |
| 包装： | 托盘 |
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Rev. B
|
Page 15 of 68
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March 2013
SDRAS
O/T (ipu)
High-Z/
driven high
SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other
SDRAM command pins, defines the operation for the SDRAM to perform.
SDCAS
O/T (ipu)
High-Z/
driven high
SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction with
other SDRAM command pins, defines the operation for the SDRAM to perform.
SDWE
O/T (ipu)
High-Z/
driven high
SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin. In conjunction with
other SDRAM command pins, defines the operation for the SDRAM to perform.
SDCKE
O/T (ipu)
High-Z/
driven high
SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK
signal. For details, see the data sheet supplied with the SDRAM device.
SDA10
O/T (ipu)
High-Z/
driven high
SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with non-SDRAM
accesses. This pin replaces the DSP’s ADDR10 pin only during SDRAM accesses.
SDDQM
O/T (ipu)
High-Z/
driven high
DQM Data Mask. SDRAM Input mask signal for write accesses and output mask signal
for read accesses. Input data is masked when DQM is sampled high during a write cycle.
The SDRAM output buffers are placed in a High-Z state when DQM is sampled high
during a read cycle. SDDQM is driven high from reset de-assertion until SDRAM initial-
ization completes. Afterwards it is driven low irrespective of whether any SDRAM
accesses occur or not.
SDCLK
O/T (ipd)
High-Z/
driving
SDRAM Clock Output. Clock driver for this pin differs from all other clock drivers. See
Figure 41 on Page 55. For models in the 100-lead package, the SDRAM interface should
be disabled to avoid unnecessary power switching by setting the DSDCTL bit in SDCTL
register. For more information, see the ADSP-214xx SHARC Processor Hardware Reference.
DAI _P20–1
I/O/T (ipu)
High-Z
Digital Applications Interface. These pins provide the physical interface to the DAI
SRU. The DAI SRU configuration registers define the combination of on-chip audio-
centric peripheral inputs or outputs connected to the pin and to the pin’s output enable.
The configuration registers of these peripherals then determines the exact behavior of
the pin. Any input or output signal present in the DAI SRU may be routed to any of these
pins.
DPI _P14–1
I/O/T (ipu)
High-Z
Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU.
The DPI SRU configuration registers define the combination of on-chip peripheral
inputs or outputs connected to the pin and to the pin’s output enable. The configu-
ration registers of these peripherals then determines the exact behavior of the pin. Any
input or output signal present in the DPI SRU may be routed to any of these pins.
WDT_CLKIN
I
Watchdog Timer Clock Input. This pin should be pulled low when not used.
WDT_CLKO
O
Watchdog Resonator Pad Output.
WDTRSTO
O (ipu)
Watchdog Timer Reset Out.
THD_P
I
Thermal Diode Anode. When not used, this pin can be left floating.
THD_M
O
Thermal Diode Cathode. When not used, this pin can be left floating.
Table 11. Pin Descriptions (Continued)
Name
Type
State
During/
After Reset
Description
The following symbols appear in the Type column of this table: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic
levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot
be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The
range of an ipd resistor can be between 31 kΩ–85kΩ. The three-state voltage of ipu pads will not reach to the full VDD_EXT level; at typical
conditions the voltage is in the range of 2.3 V to 2.7 V.
In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.
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| ADSP-21489BSWZ-4A | 功能描述:IC CCD SIGNAL PROCESSOR 100LQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21489BSWZ-4B | 功能描述:IC CCD SIGNAL PROCESSOR 176LQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21489BSWZ-AX | 制造商:Analog Devices 功能描述:X GRADE SHARC PROCESSOR - Trays |
| ADSP-21489BSWZ-BX | 制造商:Analog Devices 功能描述:X GRADE SHARC PROCESSOR - Trays |
| ADSP-21489KSWZ-3A | 功能描述:IC CCD SIGNAL PROCESSOR 100LQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
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