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| 型号： | ADSP-2191MKSTZ-160 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 16-bit Fixed-Point DSP, 160 MIPS, 160K bytes RAM; Package: 144 ld LQFP (20x20mm); No of Pins: 144; Temperature Range: Comm. |
| 中文描述： | 16-BIT, 100 MHz, OTHER DSP, PQFP144 |
| 封装： | PLASTIC, LQFP-144 |
| 文件页数： | 11/48页 |
| 文件大小： | 1789K |
| 代理商： | ADSP-2191MKSTZ-160 |
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–19–
REV. A
ADSP-2191M
ABSOLUTE MAXIMUM RATINGS
ESD SENSITIVITY
Power Dissipation
Using the operation-versus-current information in Table 8, designers can estimate the ADSP-2191M’s internal power supply (V
DDINT)
input current for a specific application, according to the formula for I
DDINT calculation beneath Table 8. For calculation of external
supply current and total supply current, see Power Dissipation on Page 40.
V
DDINT Internal (Core) Supply Voltage
1 . . . –0.3 V to +3.0 V
1Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these
or any other conditions greater than those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
V
DDEXT External (I/O) Supply Voltage . . . . –0.3 V to +4.6 V
V
IL–VIH Input Voltage . . . . . . . . . . –0.5 V to VDDEXT +0.5 V
V
OL–VOH Output Voltage Swing. . . –0.5 V to VDDEXT +0.5 V
T
STORE Storage Temperature Range . . . . . .–65C to +150C
T
LEAD Lead Temperature of ST-144 (5 seconds) . . . . 185C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the ADSP-2191M features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid perfor-
mance degradation or loss of functionality.
Table 8. Operation Types Versus Input Current
K-Grade
IDDINT(mA) CCLK = 160 MHz
B-Grade
IDDINT(mA)
1 CCLK = 140 MHz
Core
Peripheral
Core
Peripheral
Activity
Typ1
1Test conditions: V
DDINT= 2.50 V; HCLK (peripheral clock) frequency = CCLK/2 (core clock/2) frequency; TAMB = 25C.
Max2
2Test conditions: V
DDINT= 2.65 V; HCLK (peripheral clock) frequency = CCLK/2 (core clock/2) frequency; TAMB = 25C.
Typ1
Max2
Typ1
Max2
Typ1
Max2
Power Down
3
3PLL, Core, peripheral clocks, and CLKIN are disabled.
100 A
600 A
0
50 A
100 A
500 A
0
50 A
Idle 1
4
4PLL is enabled and Core and peripheral clocks are disabled.
12581247
Idle 25
5Core CLK is disabled and peripheral clock is enabled.
1260
70
1255
62
Typical6
6All instructions execute from internal memory. 50% of the instructions are repeat MACs with dual operand addressing, with changing data fetched using
a linear address sequence. 50% of the instructions are type 3 instructions.
184
210
60
70
165
185
55
62
Peak7
7All instructions execute from internal memory. 100% of the instructions are MACs with dual operand addressing, with changing data fetched using a linear
address sequence.
215
240
60
70
195
210
55
62
I
DDINT
%Typical
I
DDINT-TYPICAL
×
()
=
%Idle
I
DDINT-IDLE
×
()
%Power Down
I
DDINT-PWRDWN
×
()
++
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