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参数资料
型号： ADSP-2191MKSTZ-160
厂商： ANALOG DEVICES INC
元件分类： 数字信号处理
英文描述： 16-bit Fixed-Point DSP, 160 MIPS, 160K bytes RAM; Package: 144 ld LQFP (20x20mm); No of Pins: 144; Temperature Range: Comm.
中文描述： 16-BIT, 100 MHz, OTHER DSP, PQFP144
封装： PLASTIC, LQFP-144
文件页数： 8/48页
文件大小： 1789K
代理商： ADSP-2191MKSTZ-160
ADSP-2191M
–16–
REV. A
PF5
/SPI1SEL2
/MSEL5
I/O/T
I
Programmable Flags 5/SPI1 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 5
(during boot)
PF4
/SPI0SEL2
/MSEL4
I/O/T
I
Programmable Flags 4/SPI0 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 4
(during boot)
PF3
/SPI1SEL1
/MSEL3
I/O/T
I
Programmable Flags 3/SPI1 Slave Select output 1 (when SPI0 enabled)/Multiplier Select 3
(during boot)
PF2
/SPI0SEL1
/MSEL2
I/O/T
I
Programmable Flags 2/SPI0 Slave Select output 1 (when SPI0 enabled)/Multiplier Select 2
(during boot)
PF1
/SPISS1
/MSEL1
I/O/T
I
Programmable Flags 1/SPI1 Slave Select input (when SPI1 enabled)/Multiplier Select 1
(during boot)
PF0
/SPISS0
/MSEL0
I/O/T
I
Programmable Flags 0/SPI0 Slave Select input (when SPI0 enabled)/Multiplier Select 0
(during boot)
RD
O/T
External Port Read Strobe
WR
O/T
External Port Write Strobe
ACK
I
External Port Access Ready Acknowledge
BMS
O/T
External Port Boot Space Select
IOMS
O/T
External Port IO Space Select
MS3–0
O/T
External Port Memory Space Selects
BR
I
External Port Bus Request
BG
OExternal Port Bus Grant
BGH
O
External Port Bus Grant Hang
HAD15–0
I/O/T
Host Port Multiplexed Address and Data Bus
HA16
I
Host Port MSB of Address Bus
HACK_P
I
Host Port ACK Polarity
HRD
I
Host Port Read Strobe
HWR
I
Host Port Write Strobe
HACK
O
Host Port Access Ready Acknowledge
HALE
I
Host Port Address Latch Strobe or Address Cycle Control
HCMS
I
Host Port Internal Memory–Internal I/O Memory–Boot Memory Select
HCIOMS
I
Host Port Internal I/O Memory Select
CLKIN
I
Clock Input/Oscillator Input
XTAL
O
Oscillator Output
BMODE1–0
I
Boot Mode 1–0. The BMODE1 and BMODE0 pins have 85 k
internal pull-up resistors.
OPMODE
I
Operating Mode. The OPMODE pin has a 85 k
internal pull-up resistor.
CLKOUT
O
Clock Output
BYPASS
I
Phase-Lock-Loop (PLL) Bypass Mode. The BYPASS pin has a 85 k
internal pull-up resistor.
RCLK1–0
I/O/T
SPORT1–0 Receive Clock
RCLK2/SCK1
I/O/T
SPORT2 Receive Clock/SPI1 Serial Clock
RFS1–0
I/O/T
SPORT1–0 Receive Frame Sync
RFS2/MOSI1
I/O/T
SPORT2 Receive Frame Sync/SPI1 Master-Output, Slave-Input Data
TCLK1–0
I/O/T
SPORT1–0 Transmit Clock
TCLK2/SCK0
I/O/T
SPORT2 Transmit Clock/SPI0 Serial Clock
TFS1–0
I/O/T
SPORT1–0 Transmit Frame Sync
TFS2/MOSI0
I/O/T
SPORT2 Transmit Frame Sync/SPI0 Master-Output, Slave-Input Data
DR1–0
I/T
SPORT1–0 Serial Data Receive
DR2/MISO1
I/O/T
SPORT2 Serial Data Receive/SPI1 Master-Input, Slave-Output Data
DT1–0
O/T
SPORT1–0 Serial Data Transmit
DT2/MISO0
I/O/T
SPORT2 Serial Data Transmit/SPI0 Master-Input, Slave-Output Data
Table 7. Pin Function Descriptions (continued)
Pin
Type
Function
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