- 您现在的位置：买卖IC网 > PDF目录19473 > ADSP-BF525KBCZ-6C2 (Analog Devices Inc)IC DSP 16BIT 600MHZ 289CSPBGA PDF资料下载
参数资料
| 型号： | ADSP-BF525KBCZ-6C2 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/88页 |
| 文件大小： | 0K |
| 描述： | IC DSP 16BIT 600MHZ 289CSPBGA |
| 产品变化通告： | Datasheet Specification Change 14/Dec/2009 |
| 标准包装： | 1 |
| 系列： | Blackfin® |
| 类型： | 定点 |
| 接口： | DMA，I²C，PPI，SPI，SPORT，UART，USB |
| 时钟速率： | 600MHz |
| 非易失内存： | ROM（32 kB） |
| 芯片上RAM： | 132kB |
| 电压 - 输入/输出： | 1.8V，2.5V，3.3V |
| 电压 - 核心： | 1.10V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 289-LFBGA，CSPBGA |
| 供应商设备封装： | 289-CSPBGA（12x12） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页当前第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
System DMA access to L1 memory is not supported in
sleep mode.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals,
such as the RTC, may still be running but cannot access internal
resources or external memory. This powered-down mode can
only be exited by assertion of the reset interrupt (RESET) or by
an asynchronous interrupt generated by the RTC. When in deep
sleep mode, an RTC asynchronous interrupt causes the proces-
sor to transition to the Active mode. Assertion of RESET while
in deep sleep mode causes the processor to transition to the full
Power Savings
As shown in Table 5 , the processor supports six different power
domains, which maximizes flexibility while maintaining com-
pliance with industry standards and conventions. By isolating
the internal logic of the processor into its own power domain,
separate from the RTC and other I/O, the processor can take
advantage of dynamic power management without affecting the
RTC or other I/O devices. There are no sequencing require-
ments for the various power domains, but all domains must be
powered according to the appropriate Specifications table for
processor Operating Conditions; even if the feature/peripheral
is not used.
Table 5. Power Domains
on mode.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all of
the synchronous peripherals (SCLK). The internal voltage regu-
lator (ADSP-BF523/ADSP-BF525/ADSP-BF527 only) for the
processor can be shut off by writing b#00 to the FREQ bits of the
VR_CTL register, using the bfrom_SysControl() function. This
Power Domain
All internal logic, except RTC, Memory, USB, OTP
RTC internal logic and crystal I/O
Memory logic
USB PHY logic
OTP logic
All other I/O
V DD Range
V DDINT
V DDRTC
V DDMEM
V DDUSB
V DDOTP
V DDEXT
= -------------------------- ? ? -------------------------------- ? ? ? --------------- ?
setting sets the internal power supply voltage (V DDINT ) to 0 V to
provide the lowest static power dissipation. Any critical infor-
mation stored internally (for example, memory contents,
register contents, and other information) must be written to a
non volatile storage device prior to removing power if the pro-
cessor state is to be preserved. Writing b#00 to the FREQ bits
also causes EXT_WAKE0 and EXT_WAKE1 to transition low,
which can be used to signal an external voltage regulator to
shut down.
Since V DDEXT and V DDMEM can still be supplied in this mode, all
of the external pins three-state, unless otherwise specified. This
allows other devices that may be connected to the processor to
still have power applied without drawing unwanted current.
The Ethernet or USB modules can wake up the internal supply
regulator (ADSP-BF525 and ADSP-BF527 only) or signal an
external regulator to wake up using EXT_WAKE0 or
EXT_WAKE1. If PG15 does not connect as a PHYINT signal to
an external PHY device, PG15 can be pulled low by any other
device to wake the processor up. The processor can also be
woken up by a real-time clock wakeup event or by asserting the
RESET pin. All hibernate wake-up events initiate the hardware
reset sequence. Individual sources are enabled by the VR_CTL
register. The EXT_WAKEx signals are provided to indicate the
occurrence of wake-up events.
As long as V DDEXT is applied, the VR_CTL register maintains its
state during hibernation. All other internal registers and memo-
ries, however, lose their content in the hibernate state. State
variables may be held in external SRAM or SDRAM. The
SCKELOW bit in the VR_CTL register controls whether or not
SDRAM operates in self-refresh mode, which allows it to retain
its content while the processor is in hibernate and through the
subsequent reset sequence.
The dynamic power management feature of the processor
allows both the processor’s input voltage (V DDINT ) and clock fre-
quency (f CCLK ) to be dynamically controlled.
The power dissipated by a processor is largely a function of its
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in dynamic power dissipation, while reducing the
voltage by 25% reduces dynamic power dissipation by more
than 40%. Further, these power savings are additive, in that if
the clock frequency and supply voltage are both reduced, the
power savings can be dramatic, as shown in the following
equations.
Power Savings Factor
f CCLKRED V DDINTRED 2 T RED
f CCLKNOM ? V DDINTNOM ? ? T NOM ?
% Power Savings = ? 1 – Power Savings Factor ? ? 100%
where the variables in the equations are:
f CCLKNOM is the nominal core clock frequency
f CCLKRED is the reduced core clock frequency
V DDINTNOM is the nominal internal supply voltage
V DDINTRED is the reduced internal supply voltage
T NOM is the duration running at f CCLKNOM
T RED is the duration running at f CCLKRED
Rev. D |
Page 15 of 88 | July 2013
相关PDF资料 |
PDF描述 |
|---|---|
| NMH0505SC | CONV DC/DC 2W 5VIN 5VOUT SIP DL |
| IRU1207-33CSTR | IC REG LDO 3.3V 1A 8-SOIC |
| ADSP-2191MKCAZ-160 | IC DSP CONTROLLER 16BIT 144MBGA |
| DRA73-100-R | INDUCTOR HI TEMP 10UH 2.11A SMD |
| ADSP-2191MBCAZ-140 | IC DSP CONTROLLER 16BIT 144MBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-BF526BBCZ3 | 制造商:Analog Devices 功能描述: |
| ADSP-BF526BBCZ-3A | 功能描述:EMBEDDED PROCESSOR, BLACKFIN RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:Blackfin® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-BF526BBCZ-3AX | 制造商:Analog Devices 功能描述:DSP 32BIT 300MHZ 208CSPBGA - Trays |
| ADSP-BF526BBCZ-4A | 功能描述:IC DSP CTRLR 400MHZ 208CSPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:Blackfin® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-BF526BBCZ-4AX | 制造商:Analog Devices 功能描述:DSP 32BIT 400MHZ 208CSPBGA - Trays |
发布紧急采购，3分钟左右您将得到回复。