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参数资料
| 型号： | ADSP-BF525KBCZ-6C2 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 20/88页 |
| 文件大小： | 0K |
| 描述： | IC DSP 16BIT 600MHZ 289CSPBGA |
| 产品变化通告： | Datasheet Specification Change 14/Dec/2009 |
| 标准包装： | 1 |
| 系列： | Blackfin® |
| 类型： | 定点 |
| 接口： | DMA，I²C，PPI，SPI，SPORT，UART，USB |
| 时钟速率： | 600MHz |
| 非易失内存： | ROM（32 kB） |
| 芯片上RAM： | 132kB |
| 电压 - 输入/输出： | 1.8V，2.5V，3.3V |
| 电压 - 核心： | 1.10V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 289-LFBGA，CSPBGA |
| 供应商设备封装： | 289-CSPBGA（12x12） |
| 包装： | 托盘 |
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ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
signal. When using HWAIT, the host must still check
ALLOW_CONFIG at least once before beginning to con-
figure the Host DMA Port. After completing the
configuration, the host is required to poll the READY bit in
HOST_STATUS before beginning to transfer data. When
the host sends an HIRQ control command, the boot kernel
issues a CALL instruction to address 0xFFA0 0000. It is the
host's responsibility to ensure that valid code has been
placed at this address. The routine at 0xFFA0 0000 can be a
simple initialization routine to configure internal
resources, such as the SDRAM controller, which then
returns using an RTS instruction. The routine may also by
the final application, which will never return to the boot
kernel.
? Boot from 8-Bit Host DMA (BMODE = 0xF) — In this
mode, the Host DMA port is configured in 8-bit interrupt
mode, with little endian data formatting. Unlike other
modes, the host is responsible for interpreting the boot
stream. It writes data blocks individually into the Host
DMA port. Before configuring the DMA settings for each
block, the host may either poll the ALLOW_CONFIG bit in
HOST_STATUS or wait to be interrupted by the HWAIT
signal. When using HWAIT, the host must still check
ALLOW_CONFIG at least once before beginning to con-
figure the Host DMA Port. The host will receive an
interrupt from the HOST_ACK signal every time it is
allowed to send the next FIFO depths worth (sixteen 32-bit
words) of information. When the host sends an HIRQ con-
trol command, the boot kernel issues a CALL instruction to
address 0xFFA0 0000. It is the host's responsibility to
ensure valid code has been placed at this address. The rou-
tine at 0xFFA0 0000 can be a simple initialization routine
to configure internal resources, such as the SDRAM con-
troller, which then returns using an RTS instruction. The
routine may also by the final application, which will never
return to the boot kernel.
Table 9. Fourth Byte for Large Page Devices
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro-
vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the pro-
grammer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when com-
piling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and super-
visor (O/S kernel, device drivers, debuggers, ISRs) modes
of operation, allowing multiple levels of access to core
processor resources.
The assembly language, which takes advantage of the proces-
sor’s unique architecture, offers the following advantages:
? Seamlessly integrated DSP/MCU features are optimized for
both 8-bit and 16-bit operations.
? A multi-issue load/store modified-Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
? All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified program-
ming model.
? Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.
? Code density enhancements, which include intermixing of
16-bit and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded
in 16 bits.
DEVELOPMENT TOOLS
Analog Devices supports its processors with a complete line of
Bit Parameter
D1:D0 Page Size
(excluding spare area)
Value
00
01
10
11
Meaning
1K byte
2K byte
4K byte
8K byte
software and hardware development tools, including integrated
development environments (which include CrossCore ? Embed-
ded Studio and/or VisualDSP++ ? ), evaluation products,
emulators, and a wide variety of software add-ins.
Integrated Development Environments (IDEs)
D2
Spare Area Size
00
01
8 byte/512 byte
16 byte/512 byte
For C/C++ software writing and editing, code generation, and
debug support, Analog Devices offers two IDEs.
D5:D4 Block Size
(excluding spare area)
D6 Bus width
D3, D7 Not Used for configuration
00
01
10
11
00
01
64K byte
128K byte
256K byte
512K byte
x8
not supported
The newest IDE, CrossCore Embedded Studio, is based on the
Eclipse TM framework. Supporting most Analog Devices proces-
sor families, it is the IDE of choice for future processors,
including multicore devices. CrossCore Embedded Studio
seamlessly integrates available software add-ins to support real
time operating systems, file systems, TCP/IP stacks, USB stacks,
algorithmic software modules, and evaluation hardware board
support packages. For more information, visit www.ana-
Rev. D
|
Page 20 of 88 | July 2013
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-BF526BBCZ3 | 制造商:Analog Devices 功能描述: |
| ADSP-BF526BBCZ-3A | 功能描述:EMBEDDED PROCESSOR, BLACKFIN RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:Blackfin® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-BF526BBCZ-3AX | 制造商:Analog Devices 功能描述:DSP 32BIT 300MHZ 208CSPBGA - Trays |
| ADSP-BF526BBCZ-4A | 功能描述:IC DSP CTRLR 400MHZ 208CSPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:Blackfin® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-BF526BBCZ-4AX | 制造商:Analog Devices 功能描述:DSP 32BIT 400MHZ 208CSPBGA - Trays |
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