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| 型号： | ADSP-BF548MBBCZ-5M |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 533 MHz Blackfin Embedded Processor: ADSP-BF548MBBCZ-5M Temp Range: –40°C to +85°C Package: 400-Ball CSP_BGA BC-400-1 |
| 中文描述： | 16-BIT, 50 MHz, OTHER DSP, PBGA400 |
| 封装： | 17 X 17 MM, ROHS COMPLIANT, CSBGA-400 |
| 文件页数： | 29/100页 |
| 文件大小： | 3095K |
| 代理商： | ADSP-BF548MBBCZ-5M |
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Rev. D
|
Page 34 of 100
|
May 2011
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
ments for the ADSP-BF54x Blackfin processors’ clocks. Take
care in selecting MSEL, SSEL, and CSEL ratios so as not to
exceed the maximum core clock and system clock. Table 14
describes the phase-locked loop operating conditions.
9 SDA and SCL are 5.0V tolerant (always accept up to 5.5V maximum VIH). Voltage compliance on outputs (VOH) is limited by the VDDEXT supply voltage.
10Parameter value applies to USB_DP, USB_DM, and USB_VBUS pins. See Absolute Maximum Ratings on Page 39.
11Parameter value applies to all input and bidirectional pins, except PB1-0, PE15-14, PG15–11, and PH7-6.
12Parameter value applies to pins PG15–11 and PH7-6.
13Parameter value applies to pins PB1-0 and PE15-14. Consult the I2C specification version 2.1 for the proper resistor value and other open drain pin electrical parameters.
14TJ must be in the range: 0°C < TJ < 55°C during OTP memory programming operations.
Table 12. Core Clock (CCLK) Requirements—533 MHz and 600 MHz Speed Grade
1
Parameter
Min VDDINT
Internal Regulator Setting2
Max CCLK
Frequency
Unit
fCCLK
Core Clock Frequency
1.30 V
N/A
600
MHz
1.188 V
1.25 V
533
MHz
1.14 V
1.20 V
500
MHz
1.045 V
1.10 V
444
MHz
0.95 V
1.00 V
400
MHz
0.90 V
0.95 V
333
MHz
1 See the Ordering Guide on Page 99.
2 Use of an internal voltage regulator is not supported on automotive grade and 600 MHz speed grade models. Internal regulator setting should be used as recommended nominal
VDDINT for external regulator.
Table 13. Core Clock (CCLK) Requirements—400 MHz Speed Grade
1
Parameter
Min VDDINT
Internal Regulator Setting2
Max CCLK
Frequency
Unit
fCCLK
Core Clock Frequency
1.14 V
1.20 V
400
MHz
1.045 V
1.10 V
364
MHz
0.95 V
1.00 V
333
MHz
0.90 V
0.95 V
300
MHz
1 See Ordering Guide on Page 99.
2 Use of an internal voltage regulator is not supported on automotive grade models. Internal regulator setting should be used as recommended nominal V
DDINT for external
regulator.
Table 14. Phase-Locked Loop Operating Conditions
Parameter
Min
Max
Unit
fVCO
Voltage Controlled Oscillator (VCO) Frequency
50
Maximum fCCLK
MHz
Table 15. System Clock Requirements
Parameter
Condition
DDR SDRAM Models
Mobile DDR SDRAM Models
Unit
Max
Min
Max
fSCLK
VDDINT ≥ 1.14 V
1, Non-extended temperature grades
133
2
120
3
133
MHz
fSCLK
VDDINT < 1.14 V
1, Non-extended temperature grades
100
N/A4
N/A4
MHz
fSCLK
VDDINT ≥ 1.0 V
1, Extended temperature grade
100
N/A
MHz
1 f
SCLK must be less than or equal to fCCLK.
2 Rounded number. Actual test specification is SCLK period of 7.5 ns. See Table 25 on Page 42.
3 Rounded number. Actual test specification is SCLK period of 8.33 ns.
4 V
DDINT must be greater than or equal to 1.14 V for mobile DDR SDRAM models. See Operating Conditions on Page 33.
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相关代理商/技术参数 |
参数描述 |
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| ADSP-BF549BBCZ | 制造商:Analog Devices 功能描述: |
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| ADSP-BF561SBB500 | 功能描述:IC PROCESSOR 500MHZ 297PBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:Blackfin® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
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