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参数资料
型号： ADSP-BF548MBBCZ-5M
厂商： ANALOG DEVICES INC
元件分类： 数字信号处理
英文描述： 533 MHz Blackfin Embedded Processor: ADSP-BF548MBBCZ-5M Temp Range: –40°C to +85°C Package: 400-Ball CSP_BGA BC-400-1
中文描述： 16-BIT, 50 MHz, OTHER DSP, PBGA400
封装： 17 X 17 MM, ROHS COMPLIANT, CSBGA-400
文件页数： 58/100页
文件大小： 3095K
代理商： ADSP-BF548MBBCZ-5M
Rev. D
|
Page 60 of 100
|
May 2011
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Serial Ports Timing
Table 40 through Table 43 on Page 62 and Figure 34 on Page 61
through Figure 37 on Page 62 describe serial port operations.
Table 40. Serial Ports—External Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSE
TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)
1
3.0
ns
tHFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)1
3.0
ns
tSDRE
Receive Data Setup Before RSCLKx
1
3.0
ns
tHDRE
Receive Data Hold After RSCLKx
1
3.0
ns
tSCLKEW
TSCLKx/RSCLKx Width
4.5
ns
tSCLKE
TSCLKx/RSCLKx Period
15.0
ns
tRCLKE
RSCLKx Period
2
11.1
ns
tSUDTE
Start-Up Delay From SPORT Enable To First External TFSx
4 × tSCLKE
ns
tSUDRE
Start-Up Delay From SPORT Enable To First External RFSx
4 × tRCLKE
ns
Switching Characteristics
tDFSE
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)3
10.0
ns
tHOFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
3
0.0
ns
tDDTE
Transmit Data Delay After TSCLKx
3
10.0
ns
tHDTE
Transmit Data Hold After TSCLKx3
0.0
ns
1 Referenced to sample edge.
2 For serial port receive with external clock and external frame sync only.
3 Referenced to drive edge.
Table 41. Serial Ports—Internal Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSI
TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)
1
10.0
ns
tHFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)1
–1.5
ns
tSDRI
Receive Data Setup Before RSCLKx1
10.0
ns
tHDRI
Receive Data Hold After RSCLKx
1
–1.5
ns
Switching Characteristics
tDFSI
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2
3.0
ns
tHOFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
2
–1.0
ns
tDDTI
Transmit Data Delay After TSCLKx2
3.0
ns
tHDTI
Transmit Data Hold After TSCLKx2
–2.0
ns
tSCLKIW
TSCLKx/RSCLKx Width
4.5
ns
1 Referenced to sample edge.
2 Referenced to drive edge.
相关PDF资料
PDF描述
ADSP-BF548BBCZ-5A 533 MHz Blackfin Embedded Processor: ADSP-BF548BBCZ-5A Temp Range: –40°C to +85°C Package: 400-Ball CSP_BGA BC-400-1
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