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| 型号： | ADT7490ARQZ-R7 |
| 厂商： | ON Semiconductor |
| 文件页数： | 50/75页 |
| 文件大小： | 0K |
| 描述： | IC THERM MON FAN CTLR 24-QSOP |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi QSOP 24ld Pkg (MSL) Change 17/Jun/2010 Product Discontinuation 30/Sept/2011 |
| 标准包装： | 1,000 |
| 系列： | dBCool® |
| 功能： | 风扇控制，温度监控器 |
| 传感器类型： | 内部和外部 |
| 感应温度： | -40°C ~ 125°C |
| 精确度： | ±1.5°C（最小值） |
| 拓扑： | ADC，比较器，风扇速度计数器，多路复用器，寄存器库 |
| 输出类型： | SMBus? |
| 输出警报： | 无 |
| 输出风扇： | 是 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 24-QSOP |
| 包装： | 带卷 (TR) |
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ADT7490
Table 51. TEMPERATURE READING REGISTERS (POWER-ON DEFAULT = 0x80) (Note 1 and 2)
Register Address
0x25
0x26
0x27
R/W
Read-only
Read-only
Read-only
Description
Remote 1 Temperature Reading (Note 3 and 4) (8 MSBs of Reading)
Local Temperature Reading (8 MSBs of Reading)
Remote 2 Temperature Reading (Note 3 and 4) (8 MSBs of Reading)
1. If the extended resolution bits of these readings are also being read, the extended resolution registers (Register 0x76, Register 0x77) must
be read first. Once the extended resolution registers have been read, all associated MSB reading registers are frozen until read. Both the
extended resolution registers and the MSB registers are frozen.
2. These temperature readings can be in twos complement or Offset 64 format; this interpretation is determined by Bit 0 of Configuration
Register 5 (0x7C).
3. In twos complement mode, a temperature reading of ? 128 ? C (0x80) indicates a diode fault (open or short) on that channel.
4. In Offset 64 mode, a temperature reading of ? 64 ? C (0x00) indicates a diode fault (open or short) on that channel.
Table 52. FAN TACHOMETER READING REGISTERS (POWER-ON DEFAULT = 0x00) (Note 1)
Register Address
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
R/W
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
TACH1 Low Byte
TACH1 High Byte
TACH2 Low Byte
TACH2 High Byte
TACH3 Low Byte
TACH3 High Byte
TACH4 Low Byte
TACH4 High Byte
Description
1. These registers count the number of 11.11 m s periods (based on an internal 90 kHz clock) that occur between a number of consecutive fan TACH
pulses (default = 2). The number of TACH pulses used to count can be changed using the TACH Pulses per Revolution register (Register 0x7B).
This allows the fan speed to be accurately measured. Because a valid fan tachometer reading requires that two bytes be read, the low byte must
be read first. Both the low and high bytes are then frozen until read. At power-on, these registers contain 0x0000 until the first valid fan TACH
measurement is read into these registers. This prevents false interrupts from occurring while the fans are spinning up. A count of 0xFFFF
indicates that a fan is one of the following: stalled or blocked (object jamming the fan), failed (internal circuitry destroyed), or not populated. (The
ADT7490 expects to see a fan connected to each TACH. If a fan is not connected to that TACH, its TACH minimum high and low bytes should
be set to 0xFFFF.) An alternate function, for example, is TACH4 reconfigured as the THERM pin.
Table 53. CURRENT PWM DUTY CYCLE REGISTERS (POWER-ON DEFAULT = 0xFF) (Note 1)
Register Address
0x30
0x31
0x32
R/W
R/W
R/W
R/W
Description
PWM1 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF)
PWM2 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF)
PWM3 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF)
1. These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADT7490
reports the PWM duty cycles back through these registers. The PWM duty cycle values vary according to temperature in automatic fan speed
control mode. During fan startup, these registers report back 0x00. In manual mode, the PWM duty cycle outputs can be set to any duty cycle
value by writing to these registers.
Table 54. REGISTER 0 x33 ? PECI0 READING REGISTER (POWER-ON DEFAULT = 0x80)
Register Address
0x33
R/W
Read-only
Description
PECI0: This Register Reads the Eight Bits Representative of PECI Client Address 0x30
Table 55. PECI LIMIT R EGISTERS
Register Address
0x34
0x35
R/W
R/W
R/W
Description
PECI Low Limit
PECI High Limit
Power-On Default
0x81
0x00
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