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| 型号： | ADT7490ARQZ-R7 |
| 厂商： | ON Semiconductor |
| 文件页数： | 53/75页 |
| 文件大小： | 0K |
| 描述： | IC THERM MON FAN CTLR 24-QSOP |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi QSOP 24ld Pkg (MSL) Change 17/Jun/2010 Product Discontinuation 30/Sept/2011 |
| 标准包装： | 1,000 |
| 系列： | dBCool® |
| 功能： | 风扇控制，温度监控器 |
| 传感器类型： | 内部和外部 |
| 感应温度： | -40°C ~ 125°C |
| 精确度： | ±1.5°C（最小值） |
| 拓扑： | ADC，比较器，风扇速度计数器，多路复用器，寄存器库 |
| 输出类型： | SMBus? |
| 输出警报： | 无 |
| 输出风扇： | 是 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 24-QSOP |
| 包装： | 带卷 (TR) |
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ADT7490
Table 60. T CONTROL LIMIT REGISTER (POWER-ON DEFAULT = 0x00) (Note 1)
Register Address
0x3D
R/W (Note 2)
R/W
PECI T CONTROL Limit
Description
1. If any PECI reading exceeds the T CONTROL limit, all PWM outputs drive their fans at 100% duty cycle. This is a fail-safe mechanism
incorporated to cool the system in the event of a critical overtemperature. It also ensures some level of cooling in the event that software
or hardware locks up. If set to 0x80, this feature is disabled. The PWM output remains at 100% until the temperature drops below
T CONTROL limit ? hysteresis.
2. This register becomes read-only when the Configuration Register 1 (0x40) Lock bit is set to 1. Any further attempts to write to this register
have no effect.
Table 61. REGISTER 0x3F ? VERSION REGISTER
Bit No.
[1:0]
[2]
[3]
[7:4]
Mnemonic
REV[1:0]
PECI
4-wire
VER[3:0]
R/W
Read-only
Read-only
Read-only
Read-only
Description
These two bits indicate the ADT7490 silicon revision number. 0x00 indicates Revision 0,
0x01 indicates Revision 1, and so on. 0x11 indicates that further revision information can be
found in the “Extended Revision” register (0x12). The revision number is then found by
adding 0x11 to the contents of the extended revision register.
This bit is set to 1 indicating that the ADT7490 supports the PECI interface.
This bit is set to 1 indicating that the ADT7490 may be configured to drive 4-wire fans using
high frequency PWM.
These bits indicate the version number of the device. This is set to 6, indicating that the
ADT7490 is part of the Heceta 6 ASIC family.
Table 62. REGISTER 0x40 ? CONFIGURATION REGISTER 1 (POWER-ON DEFAULT = 0x04)
Bit No.
[0]
[1]
[2]
[3]
[4]
[5]
[7:6]
Mnemonic
STRT
(Notes 2, 3)
LOCK
RDY
Fan Boost
PECI
Monitor
THERM in
Manual
RES
R/W (Note 1)
R/W
Write once
Read-only
R/W
R/W
R/W
Read-only
Description
Logic 1 enables monitoring and PWM control outputs based on the limit settings
programmed. Logic 0 disables monitoring and PWM control is based on the default powerup
limit settings. Note that the limit values programmed are preserved even if a Logic 0 is written
to this bit and the default settings are enabled. This bit does not become locked once Bit 1
(Lock bit) is set.
Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers
become read-only and cannot be modified until the ADT7490 is powered down and powered
up again. This prevents rogue programs such as viruses from modifying critical system limit
settings. (Lockable.)
This bit is set to 1 by the ADT7490 to indicate that the device is fully powered up and ready
to begin system monitoring.
When this bit is set to Logic 1, all PWM outputs go to 100% regardless of other fan speed
configurations and automatic fan speed control settings. When this bit is set to 0, the fan
speed control returns to the fan speed setting calculated by the preprogrammed fan speed
control settings. This bit remains writable after the Lock bit is set.
Set this bit to Logic 1 to enable CPU thermal monitoring via PECI interface. This bit becomes
read-only when the Lock bit is set.
When this bit is set to Logic 1, THERM is enabled so that the fans go to 100% duty cycle on a
THERM or T CONTROL assertion overriding any other fan setting, even when the PWMs are
configured for manual mode, or disabled. This bit becomes read-only when the Lock bit is set.
Reserved.
1. This register becomes read-only when the Configuration Register 1 (0x40) Lock bit is set to 1. Any subsequent attempts to write to this
register fail.
2. Bit 0 (STRT) of Configuration Register 1 (0x40) remains writable after the Lock bit is set.
3. When monitoring (STRT) is disabled, PWM outputs always go to 100% for thermal protection.
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