参数资料
型号: AFE7222EVM
厂商: Texas Instruments
文件页数: 57/106页
文件大小: 0K
描述: EVAL MODULE FOR AFE7222
标准包装: 1
主要目的: 接口,模拟前端(AFE)
嵌入式:
已用 IC / 零件: AFE7222
已供物品:
其它名称: 296-30300
AFE7222EVM-ND
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
REG_HALF_DUPLEX_THRU_PIN: Configures the PDN pin as a toggle pin between half duplex RX mode
and half duplex TX mode. When this bit is set, a ‘1’ on the PDN pin puts the device in half duplex RX
mode (TX shutdown), and a ‘0’ on the PDN pin puts the device in half duplex TX mode (RX shutdown).
5.11 LOW POWER RX CMOS MODE REGISTERS
In Low power CMOS mode, there are various ways to move output data of ADC with respect to output
clock to achieve required setup and hold time. This can be done using following register.
Register Name – CONFIG139 – Address 0x33D, Default = 0x00
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
DELAY_CLK_LP_CMOS<1:0>
DELAY_CLK_LP_CMOS<1:0>: Programmable delay for the output clock (ADC_DCLKOUT) when in low
power CMOS mode.
DELAY_CLK_LP_CMOS<1:0>
DELAY(1) (ns)
00
4*X - 0.3
01
5*X - 0.3
10
2*X - 0.3
11
3*X - 0.3
(1)
X is the unit delay programmed by CHANGE_UNIT_DELAY<2:0>
bits.
Register Name – CONFIG140 – Address 0x33F, Default = 0x00
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
DELAY_DATA_LP_CMOS<2:0>
CHANGE_UNIT_DELAY<2:0>
CHANGE_UNIT_DELAY<2:0>:
Changes
the
delay
step
for
the
DELAY_CLK_LP_CMOS
and
DELAY_DATA_LP_CMOS programming when in low power CMOS mode (MODE_LP_CMOS=’1’).
CHANGE_UNIT_DELAY<2:0>
DELAY UNIT "X" (ns)
000
1.12
001
1.5
010
0.55
011
0.9
100
1.85
101
2.2
110
1.25
111
1.62
DELAY_DATA_LP_CMOS<2:0>: Programmable delay for the output data when in low power CMOS
mode (MODE_LP_CMOS=’1’).
DELAY_DATA_LP_CMOS<2:0>
DELAY(1) (ns)
000
4*X - 0.3
001
5*X - 0.3
010
6*X - 0.3
011
7*X - 0.3
100
NA
101
1*X - 0.3
110
2*X - 0.3
111
3*X - 0.3
(1)
X is the unit delay programmed by CHANGE_UNIT_DELAY<2:0>
bits.
54
REGISTER DESCRIPTIONS
Copyright 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE7222 AFE7225
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