参数资料
型号: AFE7222EVM
厂商: Texas Instruments
文件页数: 99/106页
文件大小: 0K
描述: EVAL MODULE FOR AFE7222
标准包装: 1
主要目的: 接口,模拟前端(AFE)
嵌入式:
已用 IC / 零件: AFE7222
已供物品:
其它名称: 296-30300
AFE7222EVM-ND
TO GET INTO DIRECT ACCESS
MODE
SDATA
SCLK
SEN
AUX DAC A INPUT1
0
1
0
1
DA11 DA10
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
AUXDAC_A
AUXDAC_B
DELAY FOR FIRST UPDATE = 34 CLOCKS
DA10
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DA11
DA10
DA9
DA8
DA7
DA6
DA5
DA4
DA11
AUX DAC B INPUT1
tPER
tSETTLE
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
Therefore fastest update time:
First update = 22*25ns + 40ns = 590 ns
Subsequent update = 12*25ns = 300 ns
For the direct access mode where DAC_A and DAC_B are both written through SDATA, the timing is
shown in figure below.
Figure 10-19. Aux DAC Timing Diagram: DAC_A and DAC_B are Both Written Through SDATA
Therefore fastest update time:
First update = 34*25ns + 40ns = 890 ns
Subsequent update = 24*25ns = 600 ns
After the first Aux DAC refresh, subsequent refresh of the Aux DAC outputs in the above mentioned direct
access mode takes place after every 24 clocks. Note that the Aux DAC takes about 12 mA on
AVDD3_AUX (when full scale output is set to 5 mA each Aux DAC).
10.11 Full Duplex Operation – Coupling Considerations
When operating the transmit and receive channels simultaneously, several factors need to be considered
in order to minimize the coupling between the transmit and receive channels. In a general case, the DAC
and ADC clocks can be at arbitrary rates, with or without harmonic relations to each other. In such a case,
there exist serious possibilities of coupling between the ADC and DAC. As far as possible, we recommend
driving the ADC and DAC with the same clock rate externally, and use the internal clock division and
multiplication to adjust to the required ADC and DAC clock rates internally.
The internal block diagram of the clocking path is repeated below.
92
DIGITAL INTERFACE
Copyright 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE7222 AFE7225
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