参数资料
型号: AGLE3000V2-FFG484C
元件分类: FPGA
英文描述: FPGA, 75264 CLBS, 3000000 GATES, PBGA484
封装: 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, FBGA-484
文件页数: 132/156页
文件大小: 5023K
代理商: AGLE3000V2-FFG484C
IGLOOe DC and Switching Characteristics
Ad vance v0.3
2-63
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is handled by the Actel Designer software
when the user instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output
Register (OutReg), Enable Register (EnReg), and DDR. However, there is no support for
bidirectional I/Os or tristates with the LVPECL standards.
LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It
requires that one data bit be carried through two signal lines, so two pins are needed. It also
requires external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in
Figure 2-23. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one
receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.
The values for the three driver resistors are different from those used in the LVPECL
implementation because the output standard specifications are different.
Along with LVDS I/O, IGLOOe also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)
configuration (up to 40 nodes).
Figure 2-23 LVDS Circuit Diagram and Board-Level Implementation
140
Ω
100
Ω
Z0 = 50 Ω
165
Ω
165
Ω
+
P
N
P
N
INBUF_LVDS
OUTBUF_LVDS
FPGA
Bourns Part Number: CAT16-LV4F12
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