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参数资料
型号： AGLE3000V2-FFG484C
元件分类： FPGA
英文描述： FPGA, 75264 CLBS, 3000000 GATES, PBGA484
封装： 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, FBGA-484
文件页数： 77/156页
文件大小： 5023K
代理商： AGLE3000V2-FFG484C
IGLOOe DC and Switching Characteristics
Ad vance v0.3
2-13
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For
more accurate and detailed power estimations, use the SmartPower tool in the Libero IDE
software.
The power calculation methodology described below uses the following variables:
The number of PLLs as well as the number and the frequency of each output clock
generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-18 on
page 2-15.
Enable rates of output buffers—guidelines are provided for typical applications in
Table 2-19 on page 2-15.
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-19 on page 2-15. The calculation should be repeated for each clock domain defined
in the design.
Methodology
Total Power Consumption—PTOTAL
PTOTAL = PSTAT + PDYN
PSTAT is the total static power consumption.
PDYN is the total dynamic power consumption.
Total Static Power Consumption—PSTAT
PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS * PDC5 + NINPUTS* PDC6 + NOUTPUTS* PDC7
NINPUTS is the number of I/O input buffers used in the design.
NOUTPUTS is the number of I/O output buffers used in the design.
NBANKS is the number of I/O banks powered in the design.
Total Dynamic Power Consumption—PDYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock Contribution—PCLOCK
PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK
NSPINE is the number of global spines used in the user design—guidelines are provided
in Table 2-18 on page 2-15.
NROW is the number of VersaTile rows used in the design—guidelines are provided in
Table 2-18 on page 2-15
.
FCLK is the global clock signal frequency.
NS-CELL is the number of VersaTiles used as sequential modules in the design.
PAC1, PAC2, PAC3, and PAC4 are device-dependent.
Sequential Cells Contribution—PS-CELL
PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a
multi-tile sequential cell is used, it should be accounted for as 1.
α
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-18 on
page 2-15
.
FCLK is the global clock signal frequency.
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