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参数资料
型号： AGLE3000V2-FFG484C
元件分类： FPGA
英文描述： FPGA, 75264 CLBS, 3000000 GATES, PBGA484
封装： 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, FBGA-484
文件页数： 78/156页
文件大小： 5023K
代理商： AGLE3000V2-FFG484C
IGLOOe DC and Switching Characteristics
2- 14
Advance v0.3
Combinatorial Cells Contribution—PC-CELL
PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-18 on
page 2-15
.
FCLK is the global clock signal frequency.
Routing Net Contribution—PNET
PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-18 on
page 2-15
.
FCLK is the global clock signal frequency.
I/O Input Buffer Contribution—PINPUTS
PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
α
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-18 on page 2-15.
FCLK is the global clock signal frequency.
I/O Output Buffer Contribution—POUTPUTS
POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
α
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-18 on page 2-15.
β
1 is the I/O buffer enable rate—guidelines are provided in Table 2-19 on page 2-15.
FCLK is the global clock signal frequency.
RAM Contribution—PMEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3
NBLOCKS is the number of RAM blocks used in the design.
FREAD-CLOCK is the memory read clock frequency.
β
2 is the RAM enable rate for read operations—guidelines are provided in Table 2-19
on page 2-15
.
FWRITE-CLOCK is the memory write clock frequency.
β
3 is the RAM enable rate for write operations—guidelines are provided in Table 2-19
on page 2-15
.
PLL Contribution—PPLL
PPLL = PDC4 + PAC13 * FCLKOUT
FCLKOUT is the output clock frequency.
1
1.
If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its
corresponding contribution (PAC13* FCLKOUT product) to the total PLL contribution.
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