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参数资料
| 型号： | AM29BDD160GB54DKE |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | PROM |
| 英文描述： | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| 中文描述： | 512K X 32 FLASH 2.7V PROM, 54 ns, PQFP80 |
| 封装： | PLASTIC, QFP-80 |
| 文件页数： | 7/80页 |
| 文件大小： | 3476K |
| 代理商： | AM29BDD160GB54DKE |
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Am29BDD160G
13
Versatile I/O (VIO) Control
The Versatile I/O (V
IO) control allows the host
system to set the voltage levels that the device
generates at its data outputs and the voltages
tolerated at its data inputs to the same voltage
level that is asserted on the V
IO pin.
The output voltage generated on the device is
determined based on the V
IO (VCCQ) level.
A V
IO of 1.65–1.95 volts is targeted to provide
for I/O tolerance at the 1.8 volt level.
A V
CC and VIO of 2.5–2.75 volts makes the de-
vice appear as 2.5 volt-only.
Address/Control signals are 3.6 V tolerant with the
exception of CLK.
Word/Double Word Configuration
The WORD# pin controls whether the device data I/
O pins operate in the word or double word configura-
tion. If the WORD# pin is set at V
IH, the device is in
double word configuration, DQ31–DQ0 are active
and controlled by CE# and OE#.
If the WORD# pin is set at V
IL, the device is in word
configuration, and only data I/O pins DQ15–DQ0 are
active and controlled by CE# and OE#. The data I/O
pins DQ31–DQ16 are tri-stated.
Requirements for Reading Array Data
To read array data from the outputs, the sys-
tem must drive the CE# and OE# pins to V
IL.
CE# is the power control and selects the de-
vice. OE# is the output control and gates array
data to the output pins. WE# should remain at
V
IH.
The internal state machine is set for reading array
data upon device power-up, or after a hardware re-
set. This ensures that no spurious alteration of the
memory content occurs during the power transition.
No command is necessary in this mode to obtain
array data. Standard microprocessor read cycles that
assert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
Address access time (t
ACC) is the delay from sta-
ble addresses to valid output data. The chip
enable access time (t
CE) is the delay from stable
addresses and stable CE# to valid data at the
output pins. The output enable access time (t
OE)
is the delay from the falling edge of OE# to
valid data at the output pins (assuming the ad-
dresses have been stable for at least t
ACC–tOE
time and CE# has been asserted for at least
t
CE–tOE time).
See “Reading Array Data” for more information.
Refer to the AC Read Operations table for tim-
ing specifications and to Figure 15 for the
timing diagram. I
CC1 in the DC Characteristics
table represents the active current specification
for reading array data.
Simultaneous Read/Write Operations
Overview and Restrictions
Overview
Simultaneous Operation is an advances functionality
providing enhanced speed and flexibility with mini-
mum overhead. Simultaneous Operation does this by
allowing an operation to be executed (embedded op-
eration) in a bank (busy bank), then going to the
other bank (non-busy bank) and performing desired
operations.
The BDD160’s Simultaneous Operation has been op-
timized for applications that could most benefit from
this capability. These applications store code in the
big bank, while storing data in the small bank. The
best example of this is when a Sector Erase Opera-
tion (as an embedded operation) in the small (busy)
bank, while performing a Burst/synchronous Read
Operation in the big (non-busy) bank.
Restrictions
The BDD160’s Simultaneous Operation is tested by
executing an embedded operation in the small
(busy) bank while performing other operations in the
big (non-busy) bank. However, the opposite case is
neither tested nor valid. That is, it is not tested by
executing an embedded operation in the big (busy)
bank while performing other operations in the small
(non-busy) bank. See Table 2 Bank assignment for
Boot Bank Sector Devices.
Table 2. Bank Assignment for Boot Bank
Sector Devices
Also see Table 18, “Allowed Operations During Erase/
Program Suspend,” on page 38. Also see Table 12,
“Sector Addresses for Top Boot Sector Devices,” on
page 29 and see Table 13, “Sector Addresses for
Bottom Boot Sector Devices,” on page 30.
Simultaneous Read/Write Operations
With Zero Latency
The device is capable of reading data from one bank
of memory while programming or erasing in the
other bank of memory. An erase operation may also
be suspended to read from or program to another lo-
cation within the same bank (except the sector being
erased). Refer to the DC Characteristics table for Si-
multaneous read/write operations are valid for both
the main Flash memory array and the SecSi OTP sec-
tor. Simultaneous operation is disabled during the
CFI and Password Program/Verify operations. PPB
Top Boot Sector
Devices
Bottom Boot Sector
Devices
Bank
1
Small Bank
Big Bank
Bank
2
Big Bank
Small Bank
相关PDF资料 |
PDF描述 |
|---|---|
| AM29BDD160GB54DKF | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB54DKI | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB54DKK | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB54DPBE | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB54DPBI | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
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