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参数资料
| 型号： | AMIS30621C6217G |
| 厂商： | ON Semiconductor |
| 文件页数： | 35/59页 |
| 文件大小： | 0K |
| 描述： | IC MOTOR STEPPER DVR/CTLR 20SOIC |
| 标准包装： | 38 |
| 应用： | PWM 电机驱动器，步进电机驱动器 |
| 评估套件： | 可供 |
| 输出数： | 1 |
| 电流 - 输出： | 800mA |
| 电压 - 负载： | 6.5 V ~ 29 V |
| 电源电压： | 6.5 V ~ 29 V |
| 工作温度： | -40°C ~ 165°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC |
| 包装： | 管件 |
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AMIS ? 30621
Physical Address of the Circuit
The circuit must be provided with a physical address in
order to discriminate it from other ones on the LIN bus. This
address is coded on 7 bits, yielding the theoretical
possibility of 128 different circuits on the same bus.
Note : Pins HW0 and HW1 are 5 V digital inputs, whereas
pin HW2 is compliant with a 12 V level, e.g. it can be
connected to Vbat or GND via a terminal of the PCB. For
SetPositionShort operation: It is recommended to set
HW0 and HW1 to ’1’. If the ADM bit is set to ’1’ the PA0
MSB
LSB
bit in OTP has to programmed to ’1’. If the ADM bit is set
to ’0’, HW2 has to be set to ’1’.
LIN Frames
The LIN frames can be divided in writing and reading
AD[6:0] LIN SLAVE ADDRESS
Figure 22. 7 ? bit LIN Address
However the maximum number of nodes in a LIN
network is also limited by the physical properties of the bus
line. It is recommended to limit the number of nodes in a LIN
network to not exceed 16. Otherwise the reduced network
impedance may prohibit a fault free communication under
worst case conditions. Every additional node lowers the
network impedance by approximately three percent.
All LIN commands are using 7 ? bit addressing except
SetPositionShort where only the four least
significant address bits are used. These bits are shaded in
Figure 23. The ADMbit allows the use of
“SetPositionShort”. This give coverage for slaves with
different PA3 // HW2 addresses which are attached to the
same LIN bus.
The physical address AD[6:0] is a combination of four
OTP memory bits PA[3:0] from the OTP Memory Structure
and the hardwired address bits HW[2:0]. Depending on the
addressing mode (ADM –bit in OTP Memory Structure) the
combination is as illustrated in Figure 23.
frames. A frame is composed of an 8 ? bit Identifier followed
by 2, 4 or 8 data ? bytes and a checksum byte.
Note : the checksum is conform LIN1.3, classic checksum
calculation over only data bytes. (Checksum is an inverted
8 ? bit sum with carry over all data bytes.)
Writing frames will be used to:
? Program the OTP Memory;
? Configure the component with the stepper ? motor
parameters (current, speed, stepping ? mode, etc.);
? Provide set ? point position for the stepper ? motor;
? Control the motion state machine.
Whereas reading frames will be used to:
? Get the actual position of the stepper ? motor;
? Get status information such as error flags;
? Verify the right programming and configuration of the
component.
MSB
LSB
<ADM> = 0
HW0 HW1 HW2 PA3 PA2 PA1 PA0
Hardwired
MSB
OTP memory
LSB
<ADM> = 1
PA0 HW0 HW1 HW2 PA3 PA2 PA1
OTP memory
Hardwired
OTP memory
Figure 23. Combination of OTP and Hardwired
Address Bits in Function of ADM
http://onsemi.com
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