参数资料
型号: AT49BV6416T-70TI
厂商: ATMEL CORP
元件分类: DRAM
英文描述: 64-megabit (4M x 16) Page Mode 2.7-volt Flash Memory
中文描述: 4M X 16 FLASH 2.7V PROM, 70 ns, PDSO48
封装: 12 X 20 MM, PLASTIC, MO-142DD, TSOP1-48
文件页数: 7/30页
文件大小: 293K
代理商: AT49BV6416T-70TI
7
3451C–FLASH–2/05
AT49BV6416(T)
The toggle bit status bit should be used in conjunction with the erase/program and V
PP
status bit
as shown in the algorithm in
Figures 3-4 and
3-5
on
page 10
.
3.8.3
Erase/Program Status Bit
The device offers a status bit on I/O5 that indicates whether the program or erase operation has
exceeded a specified internal pulse count limit. If the status bit is a “1”, the device is unable to
verify that an erase or a word program operation has been successfully performed. The device
may also output a “1” on I/O5 if the system tries to program a “1” to a location that was previ-
ously programmed to a “0”. Only an erase operation can change a “0” back to a “1”. If a program
(Sector Erase) command is issued to a protected sector, the protected sector will not be pro-
grammed (erased). The device will go to a status read mode and the I/O5 status bit will be set
high, indicating the program (erase) operation did not complete as requested. Once the
erase/program status bit has been set to a “1”, the system must write the Product ID Exit com-
mand to return to the read mode. The erase/program status bit is a “0” while the erase or
program operation is still in progress. Please see
“Status Bit Table” on page 11
for more details.
3.8.4
VPP Status Bit
The AT49BV6416(T) provides a status bit on I/O3 that provides information regarding the volt-
age level of the VPP pin. During a program or erase operation, if the voltage on the VPP pin is
not high enough to perform the desired operation successfully, the I/O3 status bit will be a “1”.
Once the V
PP
status bit has been set to a “1”, the system must write the Product ID Exit com-
mand to return to the read mode. On the other hand, if the voltage level is high enough to
perform a program or erase operation successfully, the V
PP
status bit will output a “0”. Please
see
“Status Bit Table” on page 11
for more details.
3.9
Erase Suspend/Erase Resume
The Erase Suspend command allows the system to interrupt a sector erase operation and then
program or read data from a different sector within the same plane. Since this device has a mul-
tiple plane architecture, there is no need to use the erase suspend feature while erasing a sector
when you want to read data from a sector in another plane. After the Erase Suspend command
is given, the device requires a maximum time of 15 μs to suspend the erase operation. After the
erase operation has been suspended, the plane that contains the suspended sector enters the
erase-suspend-read mode. The system can then read data or program data to any other sector
within the device. An address is not required during the Erase Suspend command. During a sec-
tor erase suspend, another sector cannot be erased. To resume the sector erase operation, the
system must write the Erase Resume command. The Erase Resume command is a one-bus
cycle command, which does require the plane address. The device also supports an erase sus-
pend during a complete chip erase. While the chip erase is suspended, the user can read from
any sector within the memory that is protected. The command sequence for a chip erase sus-
pend and a sector erase suspend are the same.
3.10
Program Suspend/Program Resume
The Program Suspend command allows the system to interrupt a programming operation and
then read data from a different word within the memory. After the Program Suspend command is
given, the device requires a maximum of 10 μs to suspend the programming operation. After the
programming operation has been suspended, the system can then read from any other word
within the device. An address is not required during the program suspend operation. To resume
the programming operation, the system must write the Program Resume command. The
program suspend and resume are one-bus cycle commands. The command sequence for the
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