参数资料
型号: AT90LS2343-1SI
厂商: Atmel
文件页数: 42/63页
文件大小: 0K
描述: IC MCU 2K FLASH 1MHZ IND 8-SOIC
标准包装: 95
系列: AVR® 90LS
核心处理器: AVR
芯体尺寸: 8-位
速度: 1MHz
连通性: SPI
外围设备: 欠压检测/复位,POR,WDT
输入/输出数: 5
程序存储器容量: 2KB(1K x 16)
程序存储器类型: 闪存
EEPROM 大小: 128 x 8
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 6 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.209",5.30mm 宽)
包装: 管件
PIC16C433
DS41139B-page 46
Preliminary
2002 Microchip Technology Inc.
8.1
A/D Sampling Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 8-2. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), see
Figure 8-2. The maximum recommended imped-
ance for analog sources is 10 k
. After the analog
input channel is selected (changed), this acquisition
must be done before the conversion can be started.
To calculate the minimum acquisition time, Equation 8-1
may be used. This equation assumes that 1/2 LSb error
is used (512 steps for the A/D). The 1/2 LSb error is the
maximum error allowed for the A/D to meet its specified
resolution.
EQUATION 8-1:
A/D MINIMUM CHARGING
TIME
Example 8-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following system assumptions.
Rs = 10 k
1/2 LSb error
VDD = 5V
→ Rss = 7 k
Temperature (system max.) = 50
°C
VHOLD = 0 @ t = 0
EXAMPLE 8-1:
CALCULATING THE
MINIMUM REQUIRED
SAMPLE TIME
FIGURE 8-2:
ANALOG INPUT MODEL
V
HOLD = (VREF - (VREF/512)) (1 - e(-Tc/CHOLD(RIC + RSS + RS)))
or
Tc = -(51.2 pF)(1 k
+ RSS + RS) ln(1/511)
Note 1: The reference voltage (VREF) has no
effect on the equation, since it cancels
itself out.
2: The charge holding capacitor (CHOLD) is
not discharged after each conversion.
3: The maximum recommended impedance
for analog sources is 10 k
. This is
required to meet the pin leakage specifi-
cation.
4: After a conversion has completed, a
2.0 TAD delay must complete before
acquisition can begin again. During this
time, the holding capacitor is not con-
nected to the selected A/D input channel.
TACQ = Internal Amplifier Settling Time +
Holding Capacitor Charging Time +
Temperature Coefficient
TACQ =5
s + Tc + [(Temp - 25°C)(0.05 s/°C)]
TC
=-CHOLD (RIC + RSS + RS) ln(1/512)
-51.2 pF (1 k
+ 7 k + 10 k) ln(0.0020)
-51.2 pF (18 k
) ln(0.0020)
-0.921
s (-6.2146)
5.724
s
TACQ =5
s + 5.724 s + [(50°C - 25°C)(0.05 s/°C)]
10.724
s + 1.25 s
11.974
s
C
PIN
VA
R
S
RA
X
5 pF
V
DD
V
T = 0.6V
V
T = 0.6V
I leakage
R
IC
≤ 1k
Sampling
Switch
SS
R
SS
C
HOLD
= DAC capacitance
V
SS
6V
Sampling Switch
5V
4V
3V
2V
567 8 9 10 11
(k
)
V
DD
= 51.2 pF
± 500 nA
Legend: C
PIN
V
T
I leakage
R
IC
SS
C
HOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
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